368 lines
14 KiB
JavaScript
368 lines
14 KiB
JavaScript
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// not really femto8
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var EXAMPLE_SPEC = {
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name:'femto8',
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vars:{
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reg:{bits:2, toks:['a', 'b', 'ip', 'none']},
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unop:{bits:3, toks:['mova','movb','inc','dec','asl','lsr','rol','ror']},
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binop:{bits:3, toks:['or','and','xor','zero','add','sub','adc','sbb']},
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imm4:{bits:4},
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imm8:{bits:8},
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rel:{bits:8, iprel:true, ipofs:1},
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},
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rules:[
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{fmt:'~binop ~reg,b', bits:['00',1,'1',0]},
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{fmt:'~binop ~reg,#~imm8', bits:['01',1,'1',0,2]},
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{fmt:'~binop ~reg,[b]', bits:['11',1,'1',0]},
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{fmt:'~unop ~reg', bits:['00',1,'0',0]},
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{fmt:'mov ~reg,[b]', bits:['11',0,'0001']},
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{fmt:'zero ~reg', bits:['00',0,'1011']},
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{fmt:'lda #~imm8', bits:['01','00','0001',0]},
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{fmt:'ldb #~imm8', bits:['01','01','0001',0]},
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{fmt:'jmp ~imm8', bits:['01','10','0001',0]},
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{fmt:'sta ~imm4', bits:['1001',0]},
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{fmt:'bcc ~imm8', bits:['1010','0001',0]},
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{fmt:'bcs ~imm8', bits:['1010','0011',0]},
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{fmt:'bz ~imm8', bits:['1010','1100',0]},
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{fmt:'bnz ~imm8', bits:['1010','0100',0]},
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{fmt:'clc', bits:['10001000']},
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{fmt:'swapab', bits:['10000001']},
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{fmt:'reset', bits:['10001111']},
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]
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}
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var BEAKER8_SPEC = {
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"name": "Beaker8",
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"width": 8,
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"vars": {
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"cb": { "bits": 3, "toks": ["0", "1", "2", "4", "8", "10", "♦", "255"]},
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"cv": { "bits": 3, "toks": ["0", "1", "2", "3", "4", "5", "6", "♦"]},
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"cond": { "bits": 3, "toks": ["♦", "♦", ".z", ".nz", ".c", ".nc", ".s", ".ns"] },
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"ic": { "bits": 3 },
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"abs8": { "bits": 8 },
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"abs16": { "bits": 16, "endian": "little" },
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"rel8": { "bits": 8, "iprel": true, "ipofs": 2 }
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},
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"rules": [
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{ "fmt": "const.~cb", "bits": ["00000", 0] },
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{ "fmt": "const.b.~cb", "bits": ["00000", 0] },
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{ "fmt": "const ~abs8", "bits": ["00000110", 0] },
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{ "fmt": "const.b ~abs8", "bits": ["00000110", 0] },
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{ "fmt": "const.b ~abs8", "bits": ["00000110", 0] },
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{ "fmt": "const.w.~cb", "bits": ["00001", 0] },
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{ "fmt": "const.w ~abs16", "bits": ["00001110", 0] },
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{ "fmt": "peek.~cv", "bits": ["00010", 0] },
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{ "fmt": "peek.b.~cv", "bits": ["00010", 0] },
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{ "fmt": "peek ~abs8", "bits": ["00010111", 0] },
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{ "fmt": "peek.b ~abs8", "bits": ["00010111", 0] },
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{ "fmt": "peek.w.~cv", "bits": ["00011", 0] },
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{ "fmt": "peek.w ~abs8", "bits": ["00011111", 0] },
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{ "fmt": "drop.~cv", "bits": ["00101", 0] },
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{ "fmt": "drop ~abs8", "bits": ["00101111", 0] },
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{ "fmt": "send", "bits": ["00101000"] },
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{ "fmt": "send.b", "bits": ["00101000"] },
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{ "fmt": "send ~abs8", "bits": ["00101001", 0] },
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{ "fmt": "send.b ~abs8", "bits": ["00101001", 0] },
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{ "fmt": "send.~cb ~abs8", "bits": ["00000", 0, "00101001", 0] },
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{ "fmt": "send.b.~cb ~abs8", "bits": ["00000", 0, "00101001", 0] },
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{ "fmt": "send ~abs8, ~abs8", "bits": ["00000110", 0, "00101001", 0] },
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{ "fmt": "send.b ~abs8, ~abs8", "bits": ["00000110", 0, "00101001", 0] },
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{ "fmt": "receive", "bits": ["00101010"] },
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{ "fmt": "receive.b", "bits": ["00101010"] },
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{ "fmt": "receive.b ~abs8", "bits": ["00101011", 0] },
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{ "fmt": "copy", "bits": ["00101100"] },
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{ "fmt": "copy.b", "bits": ["00101100"] },
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{ "fmt": "copy.inc", "bits": ["00101110"] },
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{ "fmt": "copy.b.inc", "bits": ["00101110"] },
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{ "fmt": "copy.dec", "bits": ["00101111"] },
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{ "fmt": "copy.b.dec", "bits": ["00101111"] },
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{ "fmt": "read", "bits": ["00110000"] },
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{ "fmt": "read.b", "bits": ["00110000"] },
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{ "fmt": "read ~abs16", "bits": ["00110001", 0] },
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{ "fmt": "read.b ~abs16", "bits": ["00110001", 0] },
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{ "fmt": "read.inc", "bits": ["00110010"] },
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{ "fmt": "read.b.inc", "bits": ["00110010"] },
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{ "fmt": "read.dec", "bits": ["00110011"] },
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{ "fmt": "read.b.dec", "bits": ["00110011"] },
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{ "fmt": "write", "bits": ["00110100"] },
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{ "fmt": "write.b", "bits": ["00110100"] },
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{ "fmt": "write ~abs16", "bits": ["00110101", 0] },
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{ "fmt": "write.b ~abs16", "bits": ["00110101", 0] },
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{ "fmt": "write.inc", "bits": ["00110110"] },
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{ "fmt": "write.b.inc", "bits": ["00110110"] },
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{ "fmt": "write.dec", "bits": ["00110111"] },
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{ "fmt": "write.b.dec", "bits": ["00110111"] },
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{ "fmt": "read.w", "bits": ["00111000"] },
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{ "fmt": "read.w ~abs16", "bits": ["00111001", 0] },
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{ "fmt": "read.w.inc", "bits": ["00111010"] },
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{ "fmt": "read.w.dec", "bits": ["00111011"] },
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{ "fmt": "write.w", "bits": ["00111100"] },
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{ "fmt": "write.w ~abs16", "bits": ["00111101", 0] },
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{ "fmt": "write.w.inc", "bits": ["00111110"] },
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{ "fmt": "write.w.dec", "bits": ["00111111"] },
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{ "fmt": "nop", "bits": ["11100000"] },
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{ "fmt": "halt", "bits": ["11100001"] },
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{ "fmt": "break", "bits": ["11100010"] },
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{ "fmt": "di", "bits": ["11100100"] },
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{ "fmt": "ei", "bits": ["11100101"] },
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{ "fmt": "jump", "bits": ["11101000"] },
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{ "fmt": "jump ~abs16", "bits": ["11101001", 0] },
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{ "fmt": "call", "bits": ["11101010"] },
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{ "fmt": "call ~abs16", "bits": ["11101011", 0] },
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{ "fmt": "read.pc", "bits": ["11101100"] },
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{ "fmt": "djr.nz ~abs8", "bits": ["11101110"] },
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{ "fmt": "djr.b.nz ~abs8", "bits": ["11101110"] },
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{ "fmt": "djr.w.nz ~abs8", "bits": ["11101111"] },
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{ "fmt": "jr", "bits": ["11110000"] },
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{ "fmt": "jr~cond", "bits": ["11110", 0] },
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{ "fmt": "ret", "bits": ["11111000"] },
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{ "fmt": "ret~cond", "bits": ["11111", 0] }
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]
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};
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var vm = require('vm');
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var fs = require('fs');
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var assert = require('assert');
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var includeInThisContext = function(path) {
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var code = fs.readFileSync(path);
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vm.runInThisContext(code, path);
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};
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var femto8_spec = JSON.parse(fs.readFileSync('presets/verilog/femto8.json'));
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var femto16_spec = JSON.parse(fs.readFileSync('presets/verilog/femto16.json'));
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var riscv_spec = JSON.parse(fs.readFileSync('presets/verilog/riscv.json'));
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var assembler = require("gen/worker/assembler.js");
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describe('Assemble', function() {
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it('Should assemble femto8', function() {
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let source = `.arch femto8
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.org 128
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.len 128
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.define VPU_LO 8
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.define VPU_HI 9
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.define VPU_WRITE 10
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.define VPU_MOVE 11
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.define IN_FLAGS $42
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.define F_VSYNC 16
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Start:
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zero A ; comment
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sta VPU_LO
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sta VPU_HI
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sta 0
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DisplayLoop:zero B
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mov A,[b]
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sta VPU_WRITE
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sta VPU_MOVE
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lda #F_VSYNC
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ldb #IN_FLAGS
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and none,[B]
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bz DisplayLoop
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WaitVsync:
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and none,[B]
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bnz WaitVsync
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zero B
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mov A,[b]
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inc A
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sta 0
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jmp DisplayLoop
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`;
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let asm = new assembler.Assembler(EXAMPLE_SPEC);
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let result = asm.assembleFile(source);
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//console.log(result);
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//assert.equal(result, {});
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assert.equal(128, result.origin);
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assert.equal(152, result.ip);
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assert.deepEqual([], result.errors);
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assert.deepEqual({
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insns: "0B",
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line: 13,
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nbits: 8,
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offset: 128
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}, result.lines[0]);
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assert.deepEqual(
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[ { line: 13, offset: 128, nbits: 8, insns: '0B' },
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{ line: 14, offset: 129, nbits: 8, insns: '98' },
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{ line: 15, offset: 130, nbits: 8, insns: '99' },
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{ line: 16, offset: 131, nbits: 8, insns: '90' },
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{ line: 18, offset: 132, nbits: 8, insns: '1B' },
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{ line: 19, offset: 133, nbits: 8, insns: 'C1' },
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{ line: 20, offset: 134, nbits: 8, insns: '9A' },
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{ line: 21, offset: 135, nbits: 8, insns: '9B' },
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{ line: 22, offset: 136, nbits: 16, insns: '41 10' },
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{ line: 23, offset: 138, nbits: 16, insns: '51 42' },
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{ line: 24, offset: 140, nbits: 8, insns: 'F9' },
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{ line: 25, offset: 141, nbits: 16, insns: 'AC 84' },
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{ line: 27, offset: 143, nbits: 8, insns: 'F9' },
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{ line: 28, offset: 144, nbits: 16, insns: 'A4 8F' },
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{ line: 29, offset: 146, nbits: 8, insns: '1B' },
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{ line: 30, offset: 147, nbits: 8, insns: 'C1' },
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{ line: 31, offset: 148, nbits: 8, insns: '02' },
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{ line: 32, offset: 149, nbits: 8, insns: '90' },
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{ line: 33, offset: 150, nbits: 16, insns: '61 84' },
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], result.lines);
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assert.equal(11, result.output[0]);
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assert.equal(128, result.output.length);
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});
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it('Should fail', function() {
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let source = `.arch femto8
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zero C
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`;
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let asm = new assembler.Assembler(EXAMPLE_SPEC);
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let result = asm.assembleFile(source);
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assert.deepEqual(
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[ { msg: "Can't use 'c' here, only one of: a, b, ip, none", line: 2 } ],
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result.errors);
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});
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it('Should assemble femto16', function() {
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let source = `
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.arch femto16
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.org 0x8000
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.len 256
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mov sp,@$6fff
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mov dx,@Fib
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jsr dx
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reset
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Fib:
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mov ax,#1
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mov bx,#0
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Loop:
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mov cx,ax
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add ax,bx
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mov bx,cx
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push ax
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pop ax
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mov [42],ax
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mov ax,[42]
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bcc Loop
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rts
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`;
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let asm = new assembler.Assembler(femto16_spec);
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let result = asm.assembleFile(source);
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assert.deepEqual([], result.errors);
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assert.deepEqual(result.lines, [
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{ line: 5, offset: 32768, nbits: 32, insns: '1E58 6FFF' },
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{ line: 6, offset: 32770, nbits: 32, insns: '1B58 8006' },
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{ line: 7, offset: 32772, nbits: 16, insns: '771E' },
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{ line: 8, offset: 32773, nbits: 16, insns: 'B8FF' },
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{ line: 10, offset: 32774, nbits: 16, insns: 'D801' },
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{ line: 11, offset: 32775, nbits: 16, insns: 'D900' },
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{ line: 13, offset: 32776, nbits: 16, insns: '0258' },
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{ line: 14, offset: 32777, nbits: 16, insns: '0061' },
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{ line: 15, offset: 32778, nbits: 16, insns: '015A' },
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{ line: 16, offset: 32779, nbits: 16, insns: '5006' },
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{ line: 17, offset: 32780, nbits: 16, insns: '480E' },
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{ line: 18, offset: 32781, nbits: 16, insns: '302A' },
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{ line: 19, offset: 32782, nbits: 16, insns: '282A' },
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{ line: 20, offset: 32783, nbits: 16, insns: '81F8' },
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{ line: 21, offset: 32784, nbits: 16, insns: '4F0E' }
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]);
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});
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it('Should assemble riscv', function() {
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let source = `
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.arch riscv
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.org 0
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.len 2048
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.width 32
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FOO:
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add x1,x2,x2
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sub x3,zero,x2
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xor x4,x3,x2
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addi x5,x4,1234
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beq x10,x11,FOO3
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; .data 0x7cb504e3
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FOO3:
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beq x10,x11,FOO ;7CB504E3
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FOO2:
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lw x6,12(x6)
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sb x7,64(x6)
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sh x7,68(x7)
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sw x7,72(x7)
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lui x12,12
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`;
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let asm = new assembler.Assembler(riscv_spec);
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let result = asm.assembleFile(source);
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assert.deepEqual([], result.errors);
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assert.deepEqual(result.lines, [
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{ line: 7, offset: 0, nbits: 32, insns: '002100B3' },
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{ line: 8, offset: 1, nbits: 32, insns: '402001B3' },
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{ line: 9, offset: 2, nbits: 32, insns: '0021C233' },
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{ line: 10, offset: 3, nbits: 32, insns: '4D220293' },
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{ line: 11, offset: 4, nbits: 32, insns: '00B50263' },
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{ line: 14, offset: 5, nbits: 32, insns: 'FEB506E3' },
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{ line: 16, offset: 6, nbits: 32, insns: '00C32303' },
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{ line: 17, offset: 7, nbits: 32, insns: '04638023' },
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{ line: 18, offset: 8, nbits: 32, insns: '04739223' },
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{ line: 19, offset: 9, nbits: 32, insns: '0473A423' },
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{ line: 20, offset: 10, nbits: 32, insns: '0000C637' }
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]);
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});
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it('Should assemble multiword little endian constants', function() {
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let source = `
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.arch Beaker8
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.org 0
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.len 0x4000
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.define vramWrite $00
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.define vramRead $01
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.define vdpReg0 $40
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.define vdpReg1 $41
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.define vdpReg2 $42
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boot: di
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jump Init
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init: call setTextMode
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halt
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setTextMode:
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send vdpReg0, $14
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const.w $2000 ;// length
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const.w.0 ;// address
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const.w init ;// symbol
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call clrVram
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ret
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clrVram:
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send vdpReg1
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send vdpReg2
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_loop:
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const.0
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send vramWrite
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djr.w.nz _loop
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ret
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`;
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let asm = new assembler.Assembler(BEAKER8_SPEC);
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let result = asm.assembleFile(source);
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assert.deepEqual([], result.errors);
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assert.deepEqual(result.lines, [
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{ line: 13, offset: 0, nbits: 8, insns: 'E4' },
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{ line: 14, offset: 1, nbits: 24, insns: 'E9 04 00' },
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{ line: 16, offset: 4, nbits: 24, insns: 'EB 08 00' },
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{ line: 17, offset: 7, nbits: 8, insns: 'E1' },
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{ line: 20, offset: 8, nbits: 32, insns: '06 40 29 40' },
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{ line: 21, offset: 12, nbits: 24, insns: '0E 00 20' },
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{ line: 22, offset: 15, nbits: 8, insns: '08' },
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{ line: 23, offset: 16, nbits: 24, insns: '0E 04 00' },
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{ line: 24, offset: 19, nbits: 24, insns: 'EB 17 00' },
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{ line: 25, offset: 22, nbits: 8, insns: 'F8' },
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{ line: 27, offset: 23, nbits: 16, insns: '29 41' },
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{ line: 28, offset: 25, nbits: 16, insns: '29 42' },
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{ line: 31, offset: 27, nbits: 8, insns: '00' },
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{ line: 32, offset: 28, nbits: 16, insns: '29 00' },
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{ line: 33, offset: 30, nbits: 8, insns: 'EF' },
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{ line: 34, offset: 31, nbits: 8, insns: 'F8' }
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]);
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})
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});
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