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57 lines
1.4 KiB
Verilog
57 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg [15:0] m_din;
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reg [15:0] v1;
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reg [15:0] v2;
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reg [15:0] v3;
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integer nosplit;
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always @ (posedge clk) begin
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// write needed so that V3Dead doesn't kill v0..v3
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$write(" values %x %x %x\n", v1, v2, v3);
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// Locally-set 'nosplit' will prevent the if from splitting
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// in splitAlwaysAll(). This whole always block should still be
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// intact when we call splitReorderAll() which is the subject
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// of this test.
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nosplit = cyc;
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if (nosplit > 2) begin
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/* S1 */ v1 <= 16'h0;
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/* S2 */ v1 <= m_din;
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/* S3 */ if (m_din == 16'h0) begin
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/* X1 */ v2 <= v1;
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/* X2 */ v3 <= v2;
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end
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end
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// We expect to swap S2 and S3, and to swap X1 and X2.
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// We can check that this worked by the absense of dly vars
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// in the generated output; if the reorder fails (or is disabled)
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// we should see dly vars for v1 and v2.
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end
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc<=cyc+1;
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if (cyc==7) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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