mirror of
https://github.com/sehugg/8bitworkshop.git
synced 2024-06-08 23:29:42 +00:00
31 lines
626 B
Verilog
31 lines
626 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
|
|
//
|
|
// This file ONLY is placed under the Creative Commons Public Domain, for
|
|
// any use, without warranty, 2016 by Wilson Snyder.
|
|
// SPDX-License-Identifier: CC0-1.0
|
|
|
|
module t;
|
|
|
|
reg [1:0] value;
|
|
|
|
initial begin
|
|
value = 2'b00;
|
|
unique casez (value)
|
|
2'b00 : ;
|
|
2'b01 : ;
|
|
2'b1? : ;
|
|
endcase
|
|
value = 2'b11;
|
|
unique casez (value)
|
|
2'b00 : ;
|
|
2'b01 : ;
|
|
2'b1? : ;
|
|
endcase
|
|
unique casez (1'b1)
|
|
default: ;
|
|
endcase
|
|
$write("*-* All Finished *-*\n");
|
|
$finish;
|
|
end
|
|
endmodule
|