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115 lines
2.2 KiB
Verilog
115 lines
2.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg a; initial a = 1'b1;
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reg b_fc; initial b_fc = 1'b0;
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reg b_pc; initial b_pc = 1'b0;
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reg b_oh; initial b_oh = 1'b0;
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reg b_oc; initial b_oc = 1'b0;
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wire a_l = ~a;
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wire b_oc_l = ~b_oc;
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// Note we must ensure that full, parallel, etc, only fire during
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// edges (not mid-cycle), and must provide a way to turn them off.
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// SystemVerilog provides: $asserton and $assertoff.
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// verilator lint_off CASEINCOMPLETE
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always @* begin
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// Note not all tools support directives on casez's
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`ifdef ATTRIBUTES
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case ({a,b_fc}) // synopsys full_case
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`else
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case ({a,b_fc})
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`endif
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2'b0_0: ;
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2'b0_1: ;
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2'b1_0: ;
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// Note no default
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endcase
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priority case ({a,b_fc})
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2'b0_0: ;
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2'b0_1: ;
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2'b1_0: ;
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// Note no default
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endcase
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end
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always @* begin
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`ifdef ATTRIBUTES
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case (1'b1) // synopsys full_case parallel_case
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`else
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`ifdef FAILING_FULL
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case (1'b1) // synopsys parallel_case
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`else
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case (1'b1) // synopsys parallel_full
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`endif
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`endif
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a: ;
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b_pc: ;
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endcase
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end
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`ifdef NOT_YET_VERILATOR // Unsupported
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// ambit synthesis one_hot "a, b_oh"
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// cadence one_cold "a_l, b_oc_l"
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`endif
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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a <= 1'b1;
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b_fc <= 1'b0;
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b_pc <= 1'b0;
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b_oh <= 1'b0;
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b_oc <= 1'b0;
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end
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if (cyc==2) begin
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a <= 1'b0;
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b_fc <= 1'b1;
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b_pc <= 1'b1;
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b_oh <= 1'b1;
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b_oc <= 1'b1;
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end
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if (cyc==3) begin
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a <= 1'b1;
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b_fc <= 1'b0;
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b_pc <= 1'b0;
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b_oh <= 1'b0;
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b_oc <= 1'b0;
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end
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if (cyc==4) begin
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`ifdef FAILING_FULL
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b_fc <= 1'b1;
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`endif
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`ifdef FAILING_PARALLEL
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b_pc <= 1'b1;
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`endif
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`ifdef FAILING_OH
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b_oh <= 1'b1;
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`endif
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`ifdef FAILING_OC
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b_oc <= 1'b1;
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`endif
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end
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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