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27 lines
536 B
Verilog
27 lines
536 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2014 by Jonathon Donaldson.
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// SPDX-License-Identifier: CC0-1.0
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module t
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(
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input i_clk,
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input [6:0] i_input,
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output logic o_output
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);
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always_ff @(posedge i_clk)
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// verilator lint_off CASEINCOMPLETE
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case (i_input)
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7'(92+2),
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7'(92+3): o_output <= 1'b1;
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endcase
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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