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125 lines
2.4 KiB
Verilog
125 lines
2.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Some inputs we'll set to random values
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reg [6:0] addr;
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reg [6:0] e0;
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reg [5:0] e1;
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reg [5:0] e2;
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wire [7:0] data;
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reg [2:0] wrapcheck_a;
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reg [2:0] wrapcheck_b;
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test test (/*AUTOINST*/
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// Outputs
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.data (data[7:0]),
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// Inputs
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.addr (addr[6:0]),
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.e0 (e0[6:0]),
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.e1 (e1[5:0]),
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.e2 (e2[5:0]));
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always @(/*AS*/addr) begin
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case(addr[2:0])
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3'd0+3'd0: wrapcheck_a = 3'h0;
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3'd0+3'd1: wrapcheck_a = 3'h1;
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3'd0+3'd2: wrapcheck_a = 3'h2;
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3'd0+3'd3: wrapcheck_a = 3'h3;
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default: wrapcheck_a = 3'h4;
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endcase
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case(addr[2:0])
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3'd0+0: wrapcheck_b = 3'h0;
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3'd1+1: wrapcheck_b = 3'h1;
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3'd2+2: wrapcheck_b = 3'h2;
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3'd3+3: wrapcheck_b = 3'h3;
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default: wrapcheck_b = 3'h4;
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endcase
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end
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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//$write("%d %x %x %x\n", cyc, data, wrapcheck_a, wrapcheck_b);
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if (cyc==1) begin
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addr <= 7'h28;
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e0 <= 7'h11;
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e1 <= 6'h02;
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e2 <= 6'h03;
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end
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if (cyc==2) begin
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addr <= 7'h2b;
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if (data != 8'h11) $stop;
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end
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if (cyc==3) begin
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addr <= 7'h2c;
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if (data != 8'h03) $stop;
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if (wrapcheck_a != 3'h3) $stop;
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if (wrapcheck_b != 3'h4) $stop;
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end
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if (cyc==4) begin
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addr <= 7'h0;
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if (data != 8'h00) $stop;
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if (wrapcheck_a != 3'h4) $stop;
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if (wrapcheck_b != 3'h2) $stop;
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end
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if (cyc==5) begin
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if (data != 8'h00) $stop;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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/* verilator lint_off WIDTH */
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`define AI 7'h28
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module test (/*AUTOARG*/
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// Outputs
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data,
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// Inputs
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addr, e0, e1, e2
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);
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output [7:0] data;
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input [6:0] addr;
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input [6:0] e0;
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input [5:0] e1, e2;
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reg [7:0] data;
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always @(/*AS*/addr or e0 or e1 or e2)
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begin
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case (addr)
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`AI: data = {e0[6], 1'b0, e0[5:0]};
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`AI+1: data = e1;
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`AI+2,
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`AI+3: data = e2;
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default: data = 0;
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endcase
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end
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endmodule
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// Local Variables:
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// eval:(verilog-read-defines)
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// verilog-auto-sense-defines-constant: t
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// End:
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