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73 lines
1.7 KiB
Verilog
73 lines
1.7 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk, fastclk
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);
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input clk;
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input fastclk; // surefire lint_off_line UDDIXN
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integer _mode; initial _mode=0;
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reg [31:0] ord1; initial ord1 = 32'h1111;
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wire [31:0] ord2;
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reg [31:0] ord3;
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wire [31:0] ord4;
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wire [31:0] ord5;
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wire [31:0] ord6;
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wire [31:0] ord7;
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// verilator lint_off UNOPT
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t_chg_a a (
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.a(ord1), .a_p1(ord2),
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.b(ord4), .b_p1(ord5),
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.c(ord3), .c_p1(ord4),
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.d(ord6), .d_p1(ord7)
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);
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// surefire lint_off ASWEMB
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assign ord6 = ord5 + 1;
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// verilator lint_on UNOPT
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always @ (/*AS*/ord2) ord3 = ord2 + 1;
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always @ (fastclk) begin // surefire lint_off_line ALWLTR ALWMTR
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if (_mode==1) begin
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//$write("[%0t] t_chg: %d: Values: %x %x %x %x %x %x %x\n",$time,fastclk,ord1,ord2,ord3,ord4,ord5,ord6,ord7);
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//if (ord2 == 2 && ord7 != 7) $stop;
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end
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end
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always @ (posedge clk) begin
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if (_mode==0) begin
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$write("[%0t] t_chg: Running\n", $time);
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_mode<=1;
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ord1 <= 1;
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end
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else if (_mode==1) begin
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_mode<=2;
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if (ord7 !== 7) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module t_chg_a (/*AUTOARG*/
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// Outputs
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a_p1, b_p1, c_p1, d_p1,
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// Inputs
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a, b, c, d
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);
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input [31:0] a; output [31:0] a_p1; wire [31:0] a_p1 = a + 1;
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input [31:0] b; output [31:0] b_p1; wire [31:0] b_p1 = b + 1;
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input [31:0] c; output [31:0] c_p1; wire [31:0] c_p1 = c + 1;
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input [31:0] d; output [31:0] d_p1; wire [31:0] d_p1 = d + 1;
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endmodule
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