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21 lines
489 B
Verilog
21 lines
489 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2015 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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reg [32767:0] a;
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initial begin
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// verilator lint_off WIDTHCONCAT
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a = {32768{1'b1}};
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// verilator lint_on WIDTHCONCAT
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if (a[32000] != 1'b1) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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