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72 lines
1.8 KiB
Verilog
72 lines
1.8 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2004 by Jie Xu.
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// SPDX-License-Identifier: CC0-1.0
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//
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// The test was added together with the concat optimization.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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reg [31:0] in_a;
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reg [31:0] in_b;
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reg [31:0] in_c;
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reg [31:0] in_d;
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reg [31:0] in_e;
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reg [15:0] in_f;
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wire [31:0] in_g;
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assign in_g = in_a << 4;
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reg [31:0] out_x;
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reg [31:0] out_y;
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reg [31:0] out_z;
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reg [31:0] out_o;
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reg [31:0] out_p;
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reg [31:0] out_q;
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assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f};
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assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]};
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assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]};
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assign out_o = out_z | out_y;
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assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]};
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assign out_q = {{in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]}};
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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in_a <= cyc;
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in_b <= cyc + 1;
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in_c <= cyc + 3;
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in_d <= cyc + 8;
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in_e <= cyc;
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in_f <= cyc[15:0];
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if (out_x != (in_a & {2{in_f}}))
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$stop;
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if (out_y != (in_a&in_b))
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$stop;
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if (out_z != (in_e&in_d&in_c))
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$stop;
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if (out_o != (((in_a&in_b)|(in_c&in_e&in_d))))
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$stop;
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if (out_p != (in_a & {2{in_f}} | in_e))
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$stop;
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if (out_q != (in_a ^ in_g))
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$stop;
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if (cyc==100) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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