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75 lines
2.1 KiB
Verilog
75 lines
2.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [3:0] a = crc[3:0];
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wire [3:0] b = crc[19:16];
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// TEST
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wire [3:0] out1 = {a,b}[2 +: 4];
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wire [3:0] out2 = {a,b}[5 -: 4];
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wire [3:0] out3 = {a,b}[5 : 2];
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wire [0:0] out4 = {a,b}[2];
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// Aggregate outputs into a single result vector
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wire [63:0] result = {51'h0, out4, out3, out2, out1};
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initial begin
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if ({16'h1234}[0] != 1'b0) $stop;
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if ({16'h1234}[2] != 1'b1) $stop;
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if ({16'h1234}[11:4] != 8'h23) $stop;
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if ({16'h1234}[4+:8] != 8'h23) $stop;
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if ({16'h1234}[11-:8] != 8'h23) $stop;
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if ({8'h12, 8'h34}[0] != 1'b0) $stop;
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if ({8'h12, 8'h34}[2] != 1'b1) $stop;
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if ({8'h12, 8'h34}[11:4] != 8'h23) $stop;
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if ({8'h12, 8'h34}[4+:8] != 8'h23) $stop;
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if ({8'h12, 8'h34}[11-:8] != 8'h23) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc<10) begin
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sum <= '0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h4afe43fb79d7b71e
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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