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44 lines
889 B
Verilog
44 lines
889 B
Verilog
// DESCRIPTION: Verilator: Dotted reference that uses another dotted reference
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// as the select expression
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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interface foo_intf;
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logic a;
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endinterface
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function integer the_other_func (input integer val);
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return val;
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endfunction
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module t (/*AUTOARG*/);
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genvar the_genvar;
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generate
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for (the_genvar = 0; the_genvar < 4; the_genvar++) begin: foo_loop
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foo foo_inst();
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end
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endgenerate
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bar bar_inst();
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logic x;
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assign x = foo_loop[bar_inst.THE_LP].foo_inst.y;
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//localparam N = 2;
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//assign x = foo_loop[N].foo_inst.y;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module foo();
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logic y;
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endmodule
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module bar();
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localparam THE_LP = 2;
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endmodule
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