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35 lines
729 B
Verilog
35 lines
729 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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initial begin
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// Label checks
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begin : b1
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end : b1
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//
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b2 : begin
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end : b2
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// With no statements this is a NOP
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fork : f1
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join : f1
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//
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f2: fork
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join_any : f2
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//
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fork
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join_none
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// With one statement this is supported and optimized to a begin/end
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fork : fblk
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begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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join : fblk
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end
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endmodule
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