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100 lines
2.4 KiB
Verilog
100 lines
2.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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wire noswap = crc[32];
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wire nibble = crc[33];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [31:0] out; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.out (out[31:0]),
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// Inputs
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.clk (clk),
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.noswap (noswap),
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.nibble (nibble),
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.in (in[31:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {32'h0, out};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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if (sum !== 64'h89522c3f5e5ca324) $stop;
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, noswap, nibble, in
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);
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input clk;
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input noswap;
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input nibble;
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input [31:0] in;
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output [31:0] out;
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function [7:0] EndianSwap;
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input Nibble;
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input [7:0] Data;
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begin
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EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3],
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Data[4], Data[5], Data[6], Data[7] }
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: { 4'h0, Data[0], Data[1], Data[2], Data[3] });
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end
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endfunction
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assign out[31:24] = (noswap ? in[31:24]
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: EndianSwap(nibble, in[31:24]));
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assign out[23:16] = (noswap ? in[23:16]
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: EndianSwap(nibble, in[23:16]));
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assign out[15:8] = (noswap ? in[15:8]
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: EndianSwap(nibble, in[15:8]));
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assign out[7:0] = (noswap ? in[7:0]
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: EndianSwap(nibble, in[7:0]));
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endmodule
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