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55 lines
1.3 KiB
Verilog
55 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define INT_RANGE 31:0
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`define INT_RANGE 31:0 // Duplicate identical defs are OK
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`define INT_RANGE_MAX 31
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`define VECTOR_RANGE 511:0
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module t (clk);
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// verilator lint_off WIDTH
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parameter WIDTH = 16; // Must be a power of 2
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parameter WIDTH_LOG2 = 4; // set to log2(WIDTH)
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parameter USE_BS = 1; // set to 1 for enable
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input clk;
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function [`VECTOR_RANGE] func_tree_left;
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input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector
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reg [`VECTOR_RANGE] flip;
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begin
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flip = 'd0;
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func_tree_left = flip;
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end
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endfunction
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reg [WIDTH-1:0] a; // value to be shifted
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reg [WIDTH-1:0] tree_left;
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always @(a) begin : barrel_shift
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tree_left = func_tree_left (a);
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end // barrel_shift
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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a = 5;
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end
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if (cyc==2) begin
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$display ("%x\n",tree_left);
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//if (tree_left != 'd15) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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