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35 lines
932 B
Verilog
35 lines
932 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2012 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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genvar g;
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logic [1:0] mask = 0;
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generate
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for (g=0; g<2; g++)
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begin : picker
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logic block_passed = 0; // Just for visualizing V3LinkDot debug
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function [3:0] pick;
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input [3:0] randnum;
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pick = randnum+g[3:0];
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endfunction
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always @(posedge clk) begin
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if (pick(3)!=3+g[3:0]) $stop;
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else mask[g] = 1'b1;
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if (mask == 2'b11) begin // All iterations must be finished
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endgenerate
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endmodule
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