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81 lines
1.6 KiB
Verilog
81 lines
1.6 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2005 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [11:0] in_a;
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reg [31:0] sel;
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wire [2:0] out_x;
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extractor #(4,3) extractor (
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// Outputs
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.out (out_x),
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// Inputs
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.in (in_a),
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.sel (sel));
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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//$write("%d %x %x %x\n", cyc, in_a, sel, out_x);
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if (cyc==1) begin
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in_a <= 12'b001_101_111_010;
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sel <= 32'd0;
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end
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if (cyc==2) begin
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sel <= 32'd1;
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if (out_x != 3'b010) $stop;
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end
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if (cyc==3) begin
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sel <= 32'd2;
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if (out_x != 3'b111) $stop;
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end
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if (cyc==4) begin
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sel <= 32'd3;
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if (out_x != 3'b101) $stop;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module extractor (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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in, sel
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);
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parameter IN_WIDTH=8;
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parameter OUT_WIDTH=2;
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input [IN_WIDTH*OUT_WIDTH-1:0] in;
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output [OUT_WIDTH-1:0] out;
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input [31:0] sel;
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wire [OUT_WIDTH-1:0] out = selector(in,sel);
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function [OUT_WIDTH-1:0] selector;
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input [IN_WIDTH*OUT_WIDTH-1:0] inv;
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input [31:0] selv;
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integer i;
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begin
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selector = 0;
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for (i=0; i<OUT_WIDTH; i=i+1) begin
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selector[i] = inv[selv*OUT_WIDTH+i];
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end
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end
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endfunction
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endmodule
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