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34 lines
684 B
Verilog
34 lines
684 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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function int zeroed;
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endfunction
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function automatic integer what_bit;
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input [31:0] a;
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// what_bit = 0;
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for (int i = 31; i >= 0; i = i - 1) begin
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if (a[i] == 1'b1) begin
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what_bit = i;
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end
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end
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endfunction
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module t(/*AUTOARG*/);
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parameter ZERO = zeroed();
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parameter PP = what_bit(0);
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initial begin
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if (ZERO != 0) $stop;
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if (PP != 'x) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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