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46 lines
911 B
Verilog
46 lines
911 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (clk);
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input clk;
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reg [43:0] mi;
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wire [31:0] mo;
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muxtop um ( mi, mo);
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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if (cyc==1) begin
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mi <= 44'h1234567890;
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end
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if (cyc==3) begin
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if (mo !== 32'h12345678) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module muxtop (
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input [ 43:0 ] i,
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output reg [ 31:0 ] o
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);
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always @ ( i[43:0] ) // Verify we ignore ranges on always statement sense lists
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o = MUX( i[39:0] );
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function [31:0] MUX;
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input [39:0] XX ;
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begin
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MUX = XX[39:8];
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end
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endfunction
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endmodule
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