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125 lines
2.9 KiB
Verilog
125 lines
2.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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logic use_AnB;
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logic [1:0] active_command [8:0];
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logic [1:0] command_A [8:0];
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logic [1:0] command_B [8:0];
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logic [1:0] active_command2 [8:0];
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logic [1:0] command_A2 [8:0];
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logic [1:0] command_B2 [8:0];
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logic [1:0] active_command3 [1:0][2:0][3:0];
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logic [1:0] command_A3 [1:0][2:0][3:0];
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logic [1:0] command_B3 [1:0][2:0][3:0];
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logic [2:0] use_A4nB4;
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logic [8:0][1:0] active_command4;
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logic [8:0][1:0] command_A4;
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logic [8:0][1:0] command_B4;
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logic [8:0] pipe1 [7:0];
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logic [8:0] pipe1_input;
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integer cyc;
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assign active_command[8:0] = (use_AnB) ? command_A[8:0] : command_B[8:0];
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assign active_command2 = (use_AnB) ? command_A2 : command_B2;
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// Illegal to have [1:0][x:y] here - IEEE only allows single dimension slicing
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assign active_command3[1:0] = (use_AnB) ? command_A3[1:0] : command_B3[1:0];
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// Check we can cope with things other than packed arrays
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assign active_command4 = (use_A4nB4[0]) ? command_A4 : command_B4;
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always @ (posedge clk) begin
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pipe1_input <= pipe1_input + 1;
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pipe1[0] <= pipe1_input;
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pipe1[7:1] <= pipe1[6:0];
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end
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logic [3:0][13:0] iq_read_data [15:0];
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logic [3:0][13:0] iq_data;
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logic [3:0] sel;
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assign iq_data = iq_read_data[sel];
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always @ (posedge clk) begin
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sel = sel + 1;
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end
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initial begin
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cyc = 0;
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use_AnB = 0;
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for (int i = 0; i < 7; ++i) begin
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command_A[i] = 2'b00;
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command_B[i] = 2'b11;
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command_A2[i] = 2'b00;
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command_B2[i] = 2'b11;
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pipe1_input = 9'b0;
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end
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for (int i = 0; i < 2; ++i) begin
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for (int j = 0; j < 3; ++j) begin
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for (int k = 0; k < 4; ++k) begin
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command_A3[i][j][k] = 2'b00;
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command_B3[i][j][k] = 2'b11;
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end
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end
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end
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end
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always @ (posedge clk) begin
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use_AnB <= ~use_AnB;
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cyc <= cyc + 1;
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if (use_AnB) begin
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if (active_command[3] != 2'b00) begin
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$stop;
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end
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if (active_command2[3] != 2'b00) begin
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$stop;
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end
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if (active_command3[0][1][2] != 2'b00) begin
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$stop;
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end
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end
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if (!use_AnB) begin
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if (active_command[3] != 2'b11) begin
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$stop;
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end
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if (active_command2[3] != 2'b11) begin
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$stop;
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end
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end
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end
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logic [8:0] last_pipe;
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always @(posedge clk) begin
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if (cyc < 3) begin
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last_pipe <= pipe1[0];
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end
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else begin
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if (last_pipe + 1 != pipe1[0]) begin
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$stop;
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end
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else begin
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last_pipe <= pipe1[0];
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end
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end
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if (cyc > 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule : t
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