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19 lines
461 B
Verilog
19 lines
461 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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// // `uselib {dir=<lib_diry> | file=<lib_file> | libext=<file_ext> | lib=<lib_name>
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`uselib libext=.v
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s s ();
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endmodule
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module s;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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