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34 lines
675 B
Verilog
34 lines
675 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2019 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module a(in, out);
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input in;
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output out;
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assign out = !in;
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sub sub ();
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initial $display("In '%m'");
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endmodule
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module b(in, out);
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input in;
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output out;
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assign out = in;
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sub sub ();
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initial $display("In '%m'");
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endmodule
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module c(uniq_in, uniq_out);
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input uniq_in;
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output uniq_out;
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assign uniq_out = !uniq_in;
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sub sub ();
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initial $display("In '%m'");
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endmodule
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module sub;
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initial $display("In '%m'");
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endmodule
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