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52 lines
996 B
Verilog
52 lines
996 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int i;
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int j;
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reg [2:0] cyc;
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initial cyc = 0;
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always @(posedge clk) cyc <= cyc + 1;
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always @* begin
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case (cyc)
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3'b000: i = 0;
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3'b001: i = 1;
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3'b010: i = 2;
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3'b100: i = 4;
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3'b101: i = 5;
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default: i = 99;
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endcase
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end
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// Equivalent to above
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always @* begin
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case (cyc)
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3'b101: j = 5;
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3'b100: j = 4;
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3'b010: j = 2;
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3'b001: j = 1;
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3'b000: j = 0;
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default: j = 99;
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endcase
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end
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always @(posedge clk) begin
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$display("cyle %d = %d %d", cyc, i, j);
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if (cyc == 7) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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