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34 lines
759 B
Verilog
34 lines
759 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// We see Verilator assumes a 1-bit parameter is a scalar rather than a 1-bit
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// long vector. This causes the following code to fail.
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//
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// Other event drive simulators accept this.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// At this point it is ambiguous whether a is scalar or vector
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parameter a = 1'b0;
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wire b = a[0];
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// Note however b[0] is illegal.
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always @(posedge clk) begin
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if (b == 1'b0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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else begin
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$stop;
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end
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end
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endmodule
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