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57 lines
1.0 KiB
Verilog
57 lines
1.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2010 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [31:0] O_out; // From test of Test.v
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// End of automatics
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Test test (/*AUTOINST*/
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// Outputs
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.O_out (O_out[31:0]));
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initial begin
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if (O_out != 32'h4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module Test
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(
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output [31:0] O_out
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);
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test
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#(
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.pFOO(5),
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.pBAR(2)
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) U_test
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(
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.O_out(O_out)
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);
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endmodule
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module test
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#(parameter pFOO = 7,
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parameter pBAR = 3,
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parameter pBAZ = ceiling(pFOO, pBAR)
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)
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(
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output [31:0] O_out
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);
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assign O_out = pBAZ;
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function integer ceiling;
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input [31:0] x, y;
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ceiling = ((x%y == 0) ? x/y : (x/y)+1) + 1;
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endfunction
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endmodule
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