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23 lines
495 B
Verilog
23 lines
495 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t_param_first_b (/*AUTOARG*/
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// Outputs
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par, varwidth
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);
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parameter X = 1;
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parameter FIVE = 0; // Overridden
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parameter TWO = 2;
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output [4:0] par;
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output [X:0] varwidth;
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wire [4:0] par = X;
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wire [X:0] varwidth = (FIVE==5)?TWO:0;
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endmodule
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