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35 lines
824 B
Verilog
35 lines
824 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This test examines Verilator against paramter definition with functions.
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// Particularly the function takes in argument which is multi-dimentional.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Roland Kruse and Jie Xu.
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// SPDX-License-Identifier: CC0-1.0
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module test#(
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parameter size = 4,
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parameter p = sum({32'h1,32'h2,32'h3,32'h4}, size))
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(input clk,
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input logic sel,
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output [p:0] res);
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logic [p:0] cc = 'h45;
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assign res = sel ? cc : {(p+1){1'b1}};
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function integer sum;
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input [3:0][31:0] values;
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input int size;
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sum = 0;
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begin
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for (int i = 0; i < size; i ++)
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sum += values[i];
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end
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endfunction
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endmodule
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