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53 lines
1.4 KiB
Verilog
53 lines
1.4 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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sub #(.WIDTH(4)) sub4();
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sub #(.WIDTH(8)) sub8();
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logic [3:0] out4;
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logic [7:0] out8;
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initial begin
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out4 = sub4.orer(4'b1000);
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out8 = sub8.orer(8'b10000000);
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if (out4 != 4'b1011) $stop;
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if (out8 != 8'b10111111) $stop;
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out4 = sub4.orer2(4'b1000);
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out8 = sub8.orer2(8'b10000000);
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if (out4 != 4'b1001) $stop;
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if (out8 != 8'b10011111) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub;
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parameter WIDTH = 1;
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function [WIDTH-1:0] orer;
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input [WIDTH-1:0] in;
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// IEEE provices no way to override this parameter, basically it's a localparam
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parameter MASK_W = WIDTH - 2;
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localparam [MASK_W-1:0] MASK = '1;
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// verilator lint_off WIDTH
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return in | MASK;
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// verilator lint_on WIDTH
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endfunction
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function [WIDTH-1:0] orer2;
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input [WIDTH-1:0] in;
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// Same param names as other function to check we disambiguate
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// IEEE provices no way to override this parameter, basically it's a localparam
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parameter MASK_W = WIDTH - 3;
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localparam [MASK_W-1:0] MASK = '1;
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// verilator lint_off WIDTH
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return in | MASK;
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// verilator lint_on WIDTH
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endfunction
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endmodule
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