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61 lines
1002 B
Verilog
61 lines
1002 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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// SPDX-License-Identifier: CC0-1.0
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typedef logic T_t;
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module t (/*AUTOARG*/
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// Outputs
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o, o2,
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// Inputs
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i
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);
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input T_t i;
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output T_t o;
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output T_t o2;
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sub1 #(.T_t(T_t), .CHECK(1))
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sub1 (.i, .o);
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sub2 #(.T_t(T_t), .CHECK(2))
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sub2 (.i, .o(o2));
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sub1 #(T_t, 1)
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sub1b (i, o);
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sub2 #(T_t, 2)
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sub2b (i, o2);
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endmodule
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module sub1 (i,o);
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parameter type T_t = real;
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localparam type T2_t = T_t;
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parameter int CHECK = 0;
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input T_t i;
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output T2_t o;
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assign o = i;
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if (CHECK != 1) $error;
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endmodule
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module sub2
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#(
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parameter type T_t = real,
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localparam type T2_t = T_t,
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parameter int CHECK = 0
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)
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(
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input T_t i,
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output T_t o
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);
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assign o = i;
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if (CHECK != 2) $error;
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endmodule
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// Local Variables:
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// verilog-typedef-regexp: "_t$"
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// End:
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