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35 lines
742 B
Verilog
35 lines
742 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//bug505
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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parameter WIDTH = 33;
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localparam MAX_WIDTH = 11;
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localparam NUM_OUT = num_out(WIDTH);
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wire [NUM_OUT-1:0] z;
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function integer num_out;
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input integer width;
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num_out = 1;
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while ((width + num_out - 1) / num_out > MAX_WIDTH)
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num_out = num_out * 2;
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endfunction
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initial begin
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if (NUM_OUT != 4) $stop;
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if ($bits(z) != 4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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