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107 lines
2.5 KiB
Verilog
107 lines
2.5 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2018 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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Test test (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.in (in[31:0]));
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Test2 test2 (/*AUTOINST*/
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// Inputs
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.clk (clk),
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.in (in[31:0]));
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// Test loop
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Inputs
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clk, in
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);
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input clk;
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input [31:0] in;
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reg [31:0] dly0;
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reg [31:0] dly1;
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reg [31:0] dly2;
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reg [31:0] dly3;
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// If called in an assertion, sequence, or property, the appropriate clocking event.
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// Otherwise, if called in a disable condition or a clock expression in an assertion, sequence, or prop, explicit.
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// Otherwise, if called in an action block of an assertion, the leading clock of the assertion is used.
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// Otherwise, if called in a procedure, the inferred clock
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// Otherwise, default clocking
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always @(posedge clk) begin
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dly0 <= in;
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dly1 <= dly0;
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dly2 <= dly1;
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dly3 <= dly2;
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// $past(expression, ticks, expression, clocking)
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// In clock expression
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if (dly0 != $past(in)) $stop;
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if (dly0 != $past(in,1)) $stop;
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if (dly1 != $past(in,2)) $stop;
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// $sampled(expression) -> expression
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if (in != $sampled(in)) $stop;
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end
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assert property (@(posedge clk) dly0 == $past(in));
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endmodule
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module Test2 (/*AUTOARG*/
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// Inputs
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clk, in
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);
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input clk;
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input [31:0] in;
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reg [31:0] dly0;
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reg [31:0] dly1;
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always @(posedge clk) begin
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dly0 <= in;
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dly1 <= dly0;
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end
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default clocking @(posedge clk); endclocking
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assert property (@(posedge clk) $time < 40 || dly1 == $past(in, 2));
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endmodule
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