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62 lines
1.3 KiB
Verilog
62 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2008 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/10ps
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`verilog
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`suppress_faults
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`nosuppress_faults
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`enable_portfaults
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`disable_portfaults
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`delay_mode_distributed
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`delay_mode_path
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`delay_mode_unit
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`delay_mode_zero
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`default_decay_time 1
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`default_decay_time 1.0
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`default_decay_time infinite
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// unsupported (recommended not to): `default_trireg_strength 10
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`default_nettype wire
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// unsupported: `default_nettype tri
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// unsupported: `default_nettype tri0
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// unsupported: `default_nettype wand
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// unsupported: `default_nettype triand
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// unsupported: `default_nettype wor
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// unsupported: `default_nettype trior
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// unsupported: `default_nettype trireg
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`default_nettype none
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`autoexpand_vectornets
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`accelerate
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`noaccelerate
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`expand_vectornets
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`noexpand_vectornets
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`remove_gatenames
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`noremove_gatenames
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`remove_netnames
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`noremove_netnames
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`resetall
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// unsupported: `unconnected_drive pull1
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// unsupported: `unconnected_drive pull0
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`nounconnected_drive
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`line 100 "hallo.v" 0
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// unsupported: `uselib file=../moto_lib.v
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// unsupported: `uselib dir=../lib.dir libext=.v
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module t;
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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