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50 lines
1.1 KiB
Verilog
50 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2003-2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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// surefire lint_off NBAJAM
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input clk;
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reg [7:0] _ranit;
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reg [2:0] a;
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reg [7:0] vvector;
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reg [7:0] vvector_flip;
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// surefire lint_off STMINI
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initial _ranit = 0;
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always @ (posedge clk) begin
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a <= a + 3'd1;
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vvector[a] <= 1'b1; // This should use "old" value for a
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vvector_flip[~a] <= 1'b1; // This should use "old" value for a
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//
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//========
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if (_ranit==8'd0) begin
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_ranit <= 8'd1;
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$write("[%0t] t_select_index: Running\n", $time);
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vvector <= 0;
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vvector_flip <= 0;
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a <= 3'b1;
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end
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else _ranit <= _ranit + 8'd1;
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//
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if (_ranit==8'd3) begin
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$write("%x %x\n",vvector,vvector_flip);
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if (vvector !== 8'b0000110) $stop;
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if (vvector_flip !== 8'b0110_0000) $stop;
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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