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38 lines
896 B
Verilog
38 lines
896 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2013 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [7:0] x;
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wire [3:0] en;
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wire sel;
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wire a;
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// bug675
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generate
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genvar g_k;
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for ( g_k = 0; g_k < 8; g_k = g_k + 1 )
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begin: g_index
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always @* begin
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// Note this isn't a genif, but normal if
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// verilator lint_off SELRANGE
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if(g_k<4) begin
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x[g_k] = (sel == 1'b1) ? 1'b1 : (en[g_k] == 1'b0) ? 1'b1 : a;
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end
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else begin
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x[g_k] = (sel == 1'b0) ? 1'b1 : (en[g_k-4] == 1'b0) ? 1'b1 : a;
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end
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// verilator lint_on SELRANGE
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end
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end
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endgenerate
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endmodule
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