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143 lines
3.2 KiB
Verilog
143 lines
3.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [31:0] in = crc[31:0];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [63:0] out; // From test of Test.v
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// End of automatics
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wire reset_l = ~(cyc<15);
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wire [63:0] d = crc[63:0];
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wire [8:0] t_wa = crc[8:0];
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wire [8:0] t_addr = {crc[18:17],3'b0,crc[13:10]};
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Test test (/*AUTOINST*/
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// Outputs
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.out (out[63:0]),
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// Inputs
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.clk (clk),
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.reset_l (reset_l),
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.t_wa (t_wa[8:0]),
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.d (d[63:0]),
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.t_addr (t_addr[8:0]));
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// Aggregate outputs into a single result vector
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wire [63:0] result = {out};
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h421a41d1541ea652
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (/*AUTOARG*/
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// Outputs
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out,
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// Inputs
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clk, reset_l, t_wa, d, t_addr
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);
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input clk;
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input reset_l;
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reg [63:0] m_w0 [47:0];
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reg [63:0] m_w1 [23:0];
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reg [63:0] m_w2 [23:0];
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reg [63:0] m_w3 [23:0];
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reg [63:0] m_w4 [23:0];
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reg [63:0] m_w5 [23:0];
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input [8:0] t_wa;
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input [63:0] d;
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always @ (posedge clk) begin
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if (~reset_l) begin : blk
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integer i;
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for (i=0; i<48; i=i+1) begin
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m_w0[i] <= 64'h0;
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end
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for (i=0; i<24; i=i+1) begin
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m_w1[i] <= 64'h0;
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m_w2[i] <= 64'h0;
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m_w3[i] <= 64'h0;
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m_w4[i] <= 64'h0;
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m_w5[i] <= 64'h0;
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end
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end
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else begin
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casez (t_wa[8:6])
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3'd0: m_w0[t_wa[5:0]] <= d;
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3'd1: m_w1[t_wa[4:0]] <= d;
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3'd2: m_w2[t_wa[4:0]] <= d;
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3'd3: m_w3[t_wa[4:0]] <= d;
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3'd4: m_w4[t_wa[4:0]] <= d;
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default: m_w5[t_wa[4:0]] <= d;
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endcase
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end
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end
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input [8:0] t_addr;
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wire [63:0] t_w0 = m_w0[t_addr[5:0]];
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wire [63:0] t_w1 = m_w1[t_addr[4:0]];
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wire [63:0] t_w2 = m_w2[t_addr[4:0]];
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wire [63:0] t_w3 = m_w3[t_addr[4:0]];
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wire [63:0] t_w4 = m_w4[t_addr[4:0]];
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wire [63:0] t_w5 = m_w5[t_addr[4:0]];
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output reg [63:0] out;
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always @* begin
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casez (t_addr[8:6])
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3'd0: out = t_w0;
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3'd1: out = t_w1;
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3'd2: out = t_w2;
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3'd3: out = t_w3;
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3'd4: out = t_w4;
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default: out = t_w5;
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endcase
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end
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endmodule
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