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45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2018 by Rod Steward.
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// SPDX-License-Identifier: CC0-1.0
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module IOBUF ( input T, input I, output O, inout IO );
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assign O = IO;
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assign IO = T ? 1'bz : I;
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endmodule
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module t
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(
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input [7:0] inlines,
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output [7:0] outlines,
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inout [7:0] iolines,
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input inctrl
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);
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generate for (genvar i = 4; i < 8; i = i+1) begin: Gen_D
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IOBUF d ( .T(inctrl), .I(inlines[i]), .O(outlines[i]), .IO(iolines[i]) );
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pullup d_pup (iolines[i]);
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end
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endgenerate
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IOBUF d_0 ( .T(inctrl), .I(inlines[0]), .O(outlines[0]), .IO(iolines[0]) );
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pullup d_0_pup (iolines[0]);
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IOBUF d_1 ( .T(inctrl), .I(inlines[1]), .O(outlines[1]), .IO(iolines[1]) );
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pullup d_1_pup (iolines[1]);
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IOBUF d_2 ( .T(inctrl), .I(inlines[2]), .O(outlines[2]), .IO(iolines[2]) );
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pullup d_2_pup (iolines[2]);
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IOBUF d_3 ( .T(inctrl), .I(inlines[3]), .O(outlines[3]), .IO(iolines[3]) );
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pullup d_3_pup (iolines[3]);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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