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45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2008 by Lane Brooks.
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// SPDX-License-Identifier: CC0-1.0
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`define WIDTH 2
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module top (
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input OE1,
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input OE2,
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input [`WIDTH-1:0] A1,
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input [`WIDTH-1:0] A2,
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output [`WIDTH-1:0] Y1,
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output [`WIDTH-1:0] Y2,
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output [`WIDTH-1:0] Y3,
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output [`WIDTH**2-1:0] W);
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assign W[A1] = (OE2) ? A2[0] : 1'bz;
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assign W[A2] = (OE1) ? A2[1] : 1'bz;
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// have 2 different 'chips' drive the PAD to act like a bi-directional bus
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wire [`WIDTH-1:0] PAD;
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io_ring io_ring1 (.OE(OE1), .A(A1), .O(Y1), .PAD(PAD));
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io_ring io_ring2 (.OE(OE2), .A(A2), .O(Y2), .PAD(PAD));
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assign Y3 = PAD;
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pullup p1(PAD);
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// pulldown p1(PAD);
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wire [5:0] fill = { 4'b0, A1 };
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endmodule
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module io_ring (input OE, input [`WIDTH-1:0] A, output [`WIDTH-1:0] O, inout [`WIDTH-1:0] PAD);
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io io[`WIDTH-1:0] (.OE(OE), .I(A), .O(O), .PAD(PAD));
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endmodule
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module io (input OE, input I, output O, inout PAD);
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assign O = PAD;
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assign PAD = OE ? I : 1'bz;
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endmodule
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