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25 lines
503 B
Verilog
25 lines
503 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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real x;
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real y;
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var type(x+y) z;
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initial begin
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x = 1.2;
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y = 2.3;
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z = x + y;
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if (z != (1.2+2.3)) $stop;
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z = type(z)'(22);
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if (z != 22.0) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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