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113 lines
3.0 KiB
Verilog
113 lines
3.0 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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module foo
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#(parameter type bar = logic)
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(output int bar_size);
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localparam baz = $bits(bar);
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assign bar_size = baz;
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endmodule
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module foo_wrapper
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#(parameter bar_bits = 9)
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(output int bar_size);
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foo #(.bar (logic[bar_bits-1:0])) foo_inst (.bar_size (bar_size));
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endmodule
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module t();
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logic [7:0] qux1;
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int bar_size1;
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foo #(.bar (logic [ $bits(qux1) - 1 : 0]))
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foo_inst1 (.bar_size (bar_size1));
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logic [7:0] qux2;
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int bar_size2;
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foo #(.bar (logic [ $bits(qux2) - 1 : 0]))
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foo_inst2 (.bar_size (bar_size2));
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logic [7:0] qux3;
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int bar_size3;
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foo #(.bar (logic [ $bits(qux3) - 1 : 0]))
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foo_inst3 (.bar_size (bar_size3));
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localparam bar_bits = 13;
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int bar_size_wrapper;
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foo_wrapper #(.bar_bits (bar_bits))
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foo_wrapper_inst (.bar_size (bar_size_wrapper));
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initial begin
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if ($bits(qux1) != foo_inst1.baz) begin
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$display("%m: bits of qux1 != bits of foo_inst1.baz (%0d, %0d)",
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$bits(qux1), foo_inst1.baz);
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$stop();
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end
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if ($bits(qux2) != foo_inst2.baz) begin
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$display("%m: bits of qux2 != bits of foo_inst2.baz (%0d, %0d)",
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$bits(qux2), foo_inst2.baz);
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$stop();
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end
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if ($bits(qux3) != foo_inst3.baz) begin
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$display("%m: bits of qux3 != bits of foo_inst3.baz (%0d, %0d)",
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$bits(qux3), foo_inst3.baz);
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$stop();
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end
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if (bar_bits != foo_wrapper_inst.foo_inst.baz) begin
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$display("%m: bar_bits != bits of foo_wrapper_inst.foo_inst.baz (%0d, %0d)",
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bar_bits, foo_wrapper_inst.foo_inst.baz);
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$stop();
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end
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if (bar_size1 != $bits(qux1)) begin
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$display("%m: bar_size1 != bits of qux1 (%0d, %0d)",
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bar_size1, $bits(qux1));
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$stop();
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end
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if (bar_size2 != $bits(qux2)) begin
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$display("%m: bar_size2 != bits of qux2 (%0d, %0d)",
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bar_size2, $bits(qux2));
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$stop();
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end
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if (bar_size3 != $bits(qux3)) begin
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$display("%m: bar_size3 != bits of qux3 (%0d, %0d)",
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bar_size3, $bits(qux3));
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$stop();
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end
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if (bar_size_wrapper != bar_bits) begin
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$display("%m: bar_size_wrapper != bar_bits (%0d, %0d)",
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bar_size_wrapper, bar_bits);
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$stop();
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end
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end
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genvar m;
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generate
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for (m = 1; m <= 8; m+=1) begin : gen_m
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initial begin
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if (m != foo_inst.baz) begin
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$display("%m: m != bits of foo_inst.baz (%0d, %0d)",
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m, foo_inst.baz);
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$stop();
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end
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end
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foo #(.bar (logic[m-1:0])) foo_inst (.bar_size ());
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end
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endgenerate
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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