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27 lines
482 B
Verilog
27 lines
482 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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x,
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// Inputs
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clk
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);
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`ifdef ALLOW_UNOPT
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/*verilator lint_off UNOPTFLAT*/
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`endif
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input clk;
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output [31:0] x; // Avoid eliminating x
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reg [31:0] x;
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always @* begin
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x = x ^ $random;
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end
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endmodule
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