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33 lines
647 B
Verilog
33 lines
647 B
Verilog
// DESCRIPTION: Verilator: Simple test of unoptflat
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//
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// Simple demonstration of an UNOPTFLAT combinatorial loop, using 3 bits.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2013 by Jeremy Bennett.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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wire [2:0] x;
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assign x[1:0] = { x[0], clk };
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assign x[2:1] = x[1:0];
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always @(posedge clk or negedge clk) begin
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`ifdef TEST_VERBOSE
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$write("x = %x\n", x);
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`endif
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if (x[2] != 0) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule // t
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