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58 lines
1.9 KiB
Verilog
58 lines
1.9 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0)
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module t (/*AUTOARG*/);
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parameter int sliceddn[7:0] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107};
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parameter int slicedup[0:7] = '{'h100, 'h101, 'h102, 'h103, 'h104, 'h105, 'h106, 'h107};
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int alldn[7:0];
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int allup[0:7];
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int twodn[1:0];
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int twoup[0:1];
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initial begin
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`checkh(sliceddn[7], 'h100);
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alldn[7:0] = sliceddn[7:0];
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`checkh(alldn[7], 'h100);
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alldn[7:0] = sliceddn[0 +: 8]; // down: lsb/lo +: width
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`checkh(alldn[7], 'h100);
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alldn[7:0] = sliceddn[7 -: 8]; // down: msb/hi -: width
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`checkh(alldn[7], 'h100);
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twodn[1:0] = sliceddn[6:5];
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`checkh(twodn[1], 'h101);
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`checkh(twodn[0], 'h102);
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twodn[1:0] = sliceddn[4 +: 2];
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`checkh(twodn[1], 'h102);
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`checkh(twodn[0], 'h103);
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twodn[1:0] = sliceddn[4 -: 2];
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`checkh(twodn[1], 'h103);
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`checkh(twodn[0], 'h104);
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`checkh(slicedup[7], 'h107);
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allup[0:7] = slicedup[0:7];
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`checkh(alldn[7], 'h100);
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allup[0:7] = slicedup[0 +: 8]; // up: msb/lo +: width
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`checkh(alldn[7], 'h100);
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allup[0:7] = slicedup[7 -: 8]; // up: lsb/hi -: width
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`checkh(alldn[7], 'h100);
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twoup[0:1] = slicedup[5:6];
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`checkh(twoup[1], 'h106);
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`checkh(twoup[0], 'h105);
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twoup[0:1] = slicedup[4 +: 2];
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`checkh(twoup[1], 'h105);
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`checkh(twoup[0], 'h104);
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twoup[0:1] = slicedup[4 -: 2];
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`checkh(twoup[1], 'h104);
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`checkh(twoup[0], 'h103);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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