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45 lines
923 B
Verilog
45 lines
923 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This is to test the handling of VarXRef when the referenced VAR is
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// under a generate construction.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Jie Xu and Roland Kruse.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk, addr, res
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);
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input clk;
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input [31:0] addr;
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output [15:0] res;
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memory i_mem(.addr(addr),.dout(res));
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assign i_mem.cxrow_inst[0].cmem_xrow[0] = 16'h0;
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endmodule
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module memory(addr, dout);
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parameter CM_XROWSIZE = 256;
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parameter CM_NUMXROWS = 2;
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input [31:0] addr;
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output [15:0] dout;
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generate
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genvar g_cx;
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for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++)
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begin: cxrow_inst
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reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1];
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end
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endgenerate
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assign dout = cxrow_inst[0].cmem_xrow[addr];
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endmodule
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