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17 lines
486 B
Verilog
17 lines
486 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2020 by Geza Lore. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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module t_x_assign(
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input wire clk,
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output reg o
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);
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always @(posedge clk) begin
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if (1'bx) o <= 1'd1; else o <= 1'd0;
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end
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endmodule
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