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370 lines
9.6 KiB
Verilog
370 lines
9.6 KiB
Verilog
`include "hvsync_generator.v"
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module tank_bitmap(addr, bits);
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input [7:0] addr;
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output [7:0] bits;
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reg [15:0] bitarray[256];
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assign bits = (addr[0]) ? bitarray[addr>>1][15:8] : bitarray[addr>>1][7:0];
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initial begin/*{w:16,h:16,bpw:16,count:5}*/
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bitarray[0'h00] = 16'b11110000000;
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bitarray[0'h01] = 16'b11110000000;
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bitarray[0'h02] = 16'b1100000000;
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bitarray[0'h03] = 16'b1100000000;
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bitarray[0'h04] = 16'b111101101111000;
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bitarray[0'h05] = 16'b111101101111000;
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bitarray[0'h06] = 16'b111111111111000;
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bitarray[0'h07] = 16'b111111111111000;
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bitarray[0'h08] = 16'b111111111111000;
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bitarray[0'h09] = 16'b111111111111000;
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bitarray[0'h0a] = 16'b111111111111000;
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bitarray[0'h0b] = 16'b111100001111000;
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bitarray[0'h0c] = 16'b111100001111000;
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bitarray[0'h0d] = 16'b0;
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bitarray[0'h0e] = 16'b0;
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bitarray[0'h0f] = 16'b0;
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bitarray[0'h10] = 16'b111000000000;
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bitarray[0'h11] = 16'b1111000000000;
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bitarray[0'h12] = 16'b1111000000000;
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bitarray[0'h13] = 16'b11000000000;
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bitarray[0'h14] = 16'b11101110000;
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bitarray[0'h15] = 16'b1101110000;
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bitarray[0'h16] = 16'b111101111110000;
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bitarray[0'h17] = 16'b111101111111000;
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bitarray[0'h18] = 16'b111111111111000;
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bitarray[0'h19] = 16'b11111111111000;
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bitarray[0'h1a] = 16'b11111111111100;
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bitarray[0'h1b] = 16'b11111111111100;
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bitarray[0'h1c] = 16'b11111001111100;
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bitarray[0'h1d] = 16'b1111001110000;
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bitarray[0'h1e] = 16'b1111000000000;
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bitarray[0'h1f] = 16'b1100000000000;
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bitarray[0'h20] = 16'b0;
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bitarray[0'h21] = 16'b0;
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bitarray[0'h22] = 16'b11000011000000;
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bitarray[0'h23] = 16'b111000111100000;
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bitarray[0'h24] = 16'b111101111110000;
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bitarray[0'h25] = 16'b1110111111000;
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bitarray[0'h26] = 16'b111111111100;
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bitarray[0'h27] = 16'b11111111110;
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bitarray[0'h28] = 16'b11011111111110;
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bitarray[0'h29] = 16'b111111111111100;
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bitarray[0'h2a] = 16'b111111111001000;
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bitarray[0'h2b] = 16'b11111110000000;
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bitarray[0'h2c] = 16'b1111100000000;
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bitarray[0'h2d] = 16'b111110000000;
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bitarray[0'h2e] = 16'b11110000000;
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bitarray[0'h2f] = 16'b1100000000;
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bitarray[0'h30] = 16'b0;
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bitarray[0'h31] = 16'b0;
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bitarray[0'h32] = 16'b110000000;
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bitarray[0'h33] = 16'b100001111000000;
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bitarray[0'h34] = 16'b1110001111110000;
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bitarray[0'h35] = 16'b1111010111111100;
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bitarray[0'h36] = 16'b1111111111111111;
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bitarray[0'h37] = 16'b1111111111111;
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bitarray[0'h38] = 16'b11111111110;
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bitarray[0'h39] = 16'b101111111110;
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bitarray[0'h3a] = 16'b1111111101100;
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bitarray[0'h3b] = 16'b11111111000000;
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bitarray[0'h3c] = 16'b1111111100000;
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bitarray[0'h3d] = 16'b11111110000;
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bitarray[0'h3e] = 16'b111100000;
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bitarray[0'h3f] = 16'b1100000;
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bitarray[0'h40] = 16'b0;
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bitarray[0'h41] = 16'b0;
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bitarray[0'h42] = 16'b0;
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bitarray[0'h43] = 16'b111111111000;
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bitarray[0'h44] = 16'b111111111000;
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bitarray[0'h45] = 16'b111111111000;
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bitarray[0'h46] = 16'b111111111000;
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bitarray[0'h47] = 16'b1100001111100000;
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bitarray[0'h48] = 16'b1111111111100000;
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bitarray[0'h49] = 16'b1111111111100000;
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bitarray[0'h4a] = 16'b1100001111100000;
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bitarray[0'h4b] = 16'b111111111000;
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bitarray[0'h4c] = 16'b111111111000;
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bitarray[0'h4d] = 16'b111111111000;
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bitarray[0'h4e] = 16'b111111111000;
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bitarray[0'h4f] = 16'b0;
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end
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endmodule
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module sprite_renderer(clk, vstart, load, hstart, rom_addr, rom_bits,
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hmirror, vmirror,
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gfx, busy);
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input clk, vstart, load, hstart;
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input hmirror, vmirror;
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output [4:0] rom_addr;
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input [7:0] rom_bits;
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output gfx;
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output busy = state != WAIT_FOR_VSTART;
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reg [2:0] state;
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reg [3:0] ycount;
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reg [3:0] xcount;
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reg [15:0] outbits;
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localparam WAIT_FOR_VSTART = 0;
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localparam WAIT_FOR_LOAD = 1;
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localparam LOAD1_SETUP = 2;
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localparam LOAD1_FETCH = 3;
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localparam LOAD2_SETUP = 4;
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localparam LOAD2_FETCH = 5;
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localparam WAIT_FOR_HSTART = 6;
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localparam DRAW = 7;
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always @(posedge clk)
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begin
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case (state)
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WAIT_FOR_VSTART: begin
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ycount <= 0;
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// set a default value (blank) for pixel output
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// note: multiple non-blocking assignments are vendor-specific
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gfx <= 0;
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if (vstart) state <= WAIT_FOR_LOAD;
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end
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WAIT_FOR_LOAD: begin
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xcount <= 0;
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gfx <= 0;
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if (load) state <= LOAD1_SETUP;
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end
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LOAD1_SETUP: begin
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rom_addr <= {vmirror?~ycount:ycount, 1'b0};
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state <= LOAD1_FETCH;
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end
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LOAD1_FETCH: begin
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outbits[7:0] <= rom_bits;
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state <= LOAD2_SETUP;
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end
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LOAD2_SETUP: begin
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rom_addr <= {vmirror?~ycount:ycount, 1'b1};
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state <= LOAD2_FETCH;
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end
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LOAD2_FETCH: begin
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outbits[15:8] <= rom_bits;
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state <= WAIT_FOR_HSTART;
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end
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WAIT_FOR_HSTART: begin
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if (hstart) state <= DRAW;
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end
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DRAW: begin
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// mirror graphics left/right
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gfx <= outbits[hmirror ? ~xcount[3:0] : xcount[3:0]];
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xcount <= xcount + 1;
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if (xcount == 15) begin // pre-increment value
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ycount <= ycount + 1;
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if (ycount == 15) // pre-increment value
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state <= WAIT_FOR_VSTART; // done drawing sprite
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else
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state <= WAIT_FOR_LOAD; // done drawing this scanline
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end
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end
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endcase
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end
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endmodule
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module rotation_selector(rotation, bitmap_num, hmirror, vmirror);
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input [3:0] rotation;
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output [2:0] bitmap_num;
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output hmirror, vmirror;
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always @(*)
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case (rotation[3:2])
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0: begin
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bitmap_num = {1'b0, rotation[1:0]};
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hmirror = 0;
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vmirror = 0;
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end
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1: begin
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bitmap_num = -rotation[2:0];
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hmirror = 0;
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vmirror = 1;
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end
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2: begin
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bitmap_num = {1'b0, rotation[1:0]};
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hmirror = 1;
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vmirror = 1;
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end
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3: begin
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bitmap_num = -rotation[2:0];
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hmirror = 1;
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vmirror = 0;
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end
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endcase
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endmodule
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function signed [7:0] sin_16x4;
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input [3:0] in;
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integer y;
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case (in[1:0])
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0: y = 0;
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1: y = 3;
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2: y = 5;
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3: y = 6;
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endcase
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case (in[3:2])
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0: sin_16x4 = 8'(y);
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1: sin_16x4 = 8'(7-y);
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2: sin_16x4 = 8'(-y);
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3: sin_16x4 = 8'(y-7);
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endcase
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endfunction
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module tank_controller(clk, reset, hpos, vpos, hsync, vsync,
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sprite_addr, sprite_bits, gfx,
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switch_left, switch_right, switch_up);
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input clk;
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input reset;
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input hsync;
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input vsync;
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input [8:0] hpos;
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input [8:0] vpos;
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output [7:0] sprite_addr;
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input [7:0] sprite_bits;
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output gfx;
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input switch_left, switch_right, switch_up;
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wire hmirror, vmirror;
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wire busy;
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reg [11:0] player_x_fixed;
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wire [7:0] player_x = player_x_fixed[11:4];
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wire [3:0] player_x_frac = player_x_fixed[3:0];
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reg [11:0] player_y_fixed;
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wire [7:0] player_y = player_y_fixed[11:4];
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wire [3:0] player_y_frac = player_y_fixed[3:0];
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reg [3:0] player_rot;
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reg [3:0] player_speed = 0;
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reg [3:0] frame = 0;
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wire vstart = {1'b0,player_y} == vpos;
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wire hstart = {1'b0,player_x} == hpos;
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sprite_renderer renderer(
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.clk(clk),
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.vstart(vstart),
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.load(hsync),
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.hstart(hstart),
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.hmirror(hmirror),
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.vmirror(vmirror),
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.rom_addr(sprite_addr[4:0]),
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.rom_bits(sprite_bits),
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.gfx(gfx),
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.busy(busy));
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rotation_selector rotsel(
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.rotation(player_rot),
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.bitmap_num(sprite_addr[7:5]),
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.hmirror(hmirror),
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.vmirror(vmirror));
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always @(posedge vsync or posedge reset)
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if (reset) begin
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player_rot <= 0;
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end else begin
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frame <= frame + 1;
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// rotation
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if (frame[0]) begin
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if (switch_left)
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player_rot <= player_rot - 1;
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else if (switch_right)
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player_rot <= player_rot + 1;
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if (switch_up) begin
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if (player_speed != 15)
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player_speed <= player_speed + 1;
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end else
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player_speed <= 0;
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end
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end
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always @(posedge hsync or posedge reset)
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if (reset) begin
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player_x_fixed <= 128<<4;
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player_y_fixed <= 120<<4;
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end else begin
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// movement
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if (vpos < 9'(player_speed)) begin
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if (vpos[0])
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player_x_fixed <= player_x_fixed + 12'(sin_16x4(player_rot));
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else
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player_y_fixed <= player_y_fixed - 12'(sin_16x4(player_rot+4));
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end
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end
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endmodule
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//TODO: debouncing
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module test_top(clk, reset, hsync, vsync, rgb, switches_p1);
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input clk;
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input reset;
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output hsync;
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output vsync;
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output [2:0] rgb;
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input [7:0] switches_p1;
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wire display_on;
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wire [8:0] hpos;
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wire [8:0] vpos;
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reg [7:0] paddle_x;
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reg [7:0] paddle_y;
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hvsync_generator hvsync_gen(
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.clk(clk),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire [7:0] tank_sprite_addr;
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wire [7:0] tank_sprite_bits;
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tank_bitmap tank_bmp(
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.addr(tank_sprite_addr),
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.bits(tank_sprite_bits));
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tank_controller tank1(
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.clk(clk),
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.reset(reset),
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.hpos(hpos),
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.vpos(vpos),
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.hsync(hsync),
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.vsync(vsync),
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.sprite_addr(tank_sprite_addr),
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.sprite_bits(tank_sprite_bits),
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.gfx(tank1_gfx),
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.switch_left(switches_p1[0]),
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.switch_right(switches_p1[1]),
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.switch_up(switches_p1[2])
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);
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wire tank1_gfx;
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wire unused;
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wire r = display_on && tank1_gfx;
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wire g = display_on && tank1_gfx;
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wire b = display_on && tank1_gfx;
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assign rgb = {b,g,r};
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endmodule
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