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8bitworkshop/test/cli/verilog/t_math_div0.v
2017-11-22 09:44:57 -05:00

12 lines
201 B
Verilog

module t(y);
output [3:0] y;
// bug775
// verilator lint_off WIDTH
assign y = ((0/0) ? 1 : 2) % 0;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule