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76 lines
2.2 KiB
Verilog
76 lines
2.2 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2009 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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// verilator lint_off LITENDIAN
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wire [10:41] sel2 = crc[31:0];
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wire [10:100] sel3 = {crc[26:0],crc};
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wire out20 = sel2[{1'b0,crc[3:0]} + 11];
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wire [3:0] out21 = sel2[13 : 16];
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wire [3:0] out22 = sel2[{1'b0,crc[3:0]} + 20 +: 4];
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wire [3:0] out23 = sel2[{1'b0,crc[3:0]} + 20 -: 4];
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wire out30 = sel3[{2'b0,crc[3:0]} + 11];
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wire [3:0] out31 = sel3[13 : 16];
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wire [3:0] out32 = sel3[crc[5:0] + 20 +: 4];
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wire [3:0] out33 = sel3[crc[5:0] + 20 -: 4];
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// Aggregate outputs into a single result vector
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wire [63:0] result = {38'h0, out20, out21, out22, out23, out30, out31, out32, out33};
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reg [19:50] sel1;
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initial begin
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// Path clearing
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// 122333445
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// 826048260
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sel1 = 32'h12345678;
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if (sel1 != 32'h12345678) $stop;
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if (sel1[47 : 50] != 4'h8) $stop;
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if (sel1[31 : 34] != 4'h4) $stop;
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if (sel1[27 +: 4] != 4'h3) $stop; //==[27:30], in memory as [23:20]
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if (sel1[26 -: 4] != 4'h2) $stop; //==[23:26], in memory as [27:24]
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end
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] sels=%x,%x,%x,%x %x,%x,%x,%x\n",$time, out20,out21,out22,out23, out30,out31,out32,out33);
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$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
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sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
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if (cyc==0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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end
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else if (cyc<10) begin
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sum <= 64'h0;
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end
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else if (cyc<90) begin
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end
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else if (cyc==99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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`define EXPECTED_SUM 64'h28bf65439eb12c00
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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