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28 lines
759 B
Verilog
28 lines
759 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg [3:0] counter = 0;
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integer l2;
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function log2 (input [3:0] x);
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integer log2 = (x < 2) ? 1 : (x < 4) ? 2 : (x < 8) ? 3 : 4;
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endfunction
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always @(posedge clk) begin
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counter <= counter + 1;
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l2 <= log2(counter);
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// bug589: This failed with (%Error: Internal Error: Function not underneath a statement):
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$display("log2(%d) == %d", counter, log2(counter));
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//
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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