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53 lines
917 B
Verilog
53 lines
917 B
Verilog
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`include "hvsync_generator.v"
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/*
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A simple test pattern using the hvsync_generator module.
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12000000/15734/2
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381.33977373840091521545
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381-256-23-7 = 95
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*/
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module test_hvsync_top(clk, reset, out, led);
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input clk, reset;
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output [1:0] out;
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wire hsync;
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wire vsync;
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wire [8:0] hpos;
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wire [8:0] vpos;
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reg [5:0] frame;
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output led;
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reg clk2;
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always @(posedge clk) begin
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clk2 <= !clk2;
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end
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hvsync_generator #(256,60,40,25) hvsync_gen(
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.clk(clk2),
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.reset(reset),
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.hsync(hsync),
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.vsync(vsync),
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.display_on(display_on),
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.hpos(hpos),
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.vpos(vpos)
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);
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wire r = display_on && (((hpos&7)==0) || (((vpos+frame)&7)==0));
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wire g = display_on && vpos[4];
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wire b = display_on && hpos[4];
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assign out = (hsync||vsync) ? 0 : (1+g+(r|b));
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always @(posedge vsync) begin
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frame <= frame + 1;
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end
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assign led = frame[5];
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endmodule
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// TODO: PWM grey scales
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