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{
"version": 3,
"sources": ["../src/common/cpu/ARM.ts", "../src/machine/arm32.ts", "../src/platform/arm32.ts"],
"sourcesContent": ["/*\nFrom: https://github.com/endrift/gbajs\n\nCopyright \u00A9 2012 \u2013 2013, Jeffrey Pfau\nAll rights reserved.\n\nRedistribution and use in source and binary forms, with or without\nmodification, are permitted provided that the following conditions are met:\n\n* Redistributions of source code must retain the above copyright notice, this\n list of conditions and the following disclaimer.\n\n* Redistributions in binary form must reproduce the above copyright notice,\n this list of conditions and the following disclaimer in the documentation\n and/or other materials provided with the distribution.\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\nIMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\nARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\nPOSSIBILITY OF SUCH DAMAGE.\n*/\n\nimport { Bus, CPU, InstructionBased, SavesState } from \"../devices\";\nimport { EmuHalt } from \"../emu\";\nimport { hex } from \"../util\";\n\ninterface AddressFunction extends Function {\n writesPC? : boolean;\n fixedJump? : boolean;\n}\n\ninterface ARMIRQInterface {\n\tclear() : void;\n\tswi(opcode : number) : void;\n\tswi32(opcode : number) : void;\n\tupdateTimers() : void;\n\ttestIRQ() : void;\n}\n\ninterface ARMMemoryRegion {\n\tPAGE_MASK : number;\n\tICACHE_PAGE_BITS : number;\n\ticache : ARMMemoryPage[];\n}\n\ninterface ARMOperation {\n\tnext : ARMOperation;\n\tpage : ARMMemoryPage;\n\taddress : number;\n\topcode : number;\n}\n\ninterface ARMMemoryPage {\n\tarm : ARMOperation[];\n\tthumb : ARMOperation[];\n\tinvalid : boolean;\n}\n\ninterface ARMMMUInterface {\n\tmemory : ARMMemoryRegion[];\n\tBASE_OFFSET : number;\n\tOFFSET_MASK : number;\n\n\tload8(a: number) : number;\n\tloadU8(a: number) : number;\n\tload16(a: number) : number;\n\tloadU16(a: number) : number;\n\tload32(a: number) : number;\n\tstore8(a: number, v: number) : void;\n\tstore16(a: number, v: number) : void;\n\tstore32(a: number, v: number) : void;\n\n\twait(a: number) : void;\n\twait32(a: number) : void;\n\twaitSeq32(a: number) : void;\n\twaitMul(a: number) : void;\n\twaitMulti32(a: number, total: number) : void;\n\twaitPrefetch(a: number) : void;\n\twaitPrefetch32(a: number) : void;\n\n\taddressToPage(region: number, address: number) : number;\n\taccessPage(region: number, pageId: number) : ARMMemoryPage;\n}\n\nexport interface ARMCoreState {\n\tPC: number,\n\tSP: number,\n\tgprs: number[],\n\tmode: number,\n\tcpsrI: boolean,\n\tcpsrF: boolean,\n\tcpsrV: boolean,\n\tcpsrC: boolean,\n\tcpsrZ: boolean,\n\tcpsrN: boolean,\n\tbankedRegisters: number[][],\n\tspsr: number,\n\tbankedSPSRs: number[],\n\tcycles: number,\n\tinstructionWidth: 2 | 4\n}\n\ninterface ARMCoreType {\n\tgprs: Int32Array;\n\tPC: number;\n\tSP: number;\n\tLR: number;\n\tcycles: number;\n\tmode: number;\n\tshifterOperand: number;\n\tshifterCarryOut: number|boolean;\n\tcpsrN: number|boolean;\n\tcpsrC: number|boolean;\n\tcpsrZ: number|boolean;\n\tcpsrV: number|boolean;\n\tcpsrI: number|boolean;\n\tcpsrF: number|boolean;\n\tspsr: number;\n\tmmu: ARMMMUInterface;\n\tirq : ARMIRQInterface;\n\tinstructionWidth: 2 | 4;\n\n\thasSPSR() : boolean;\n\tunpackCPSR(v : number) : void;\n\tswitchMode(mode : number) : void;\n\tswitchExecMode(mode : number) : void;\n\tpackCPSR() : number;\n\n\tstep() : void;\n\tresetCPU(startOffset : number) : void;\n\tfreeze() : ARMCoreState;\n\tdefrost(state: ARMCoreState) : void;\n\n\traiseIRQ() : void;\n\traiseTrap(irqType? : number) : void;\n}\n\nexport enum ARMMode {\n\tMODE_ARM = 0,\n\tMODE_THUMB = 1,\n\t\n\tMODE_USER = 0x10,\n\tMODE_FIQ = 0x11,\n\tMODE_IRQ = 0x12,\n\tMODE_SUPERVISOR = 0x13,\n\tMODE_ABORT = 0x17,\n\tMODE_UNDEFINED = 0x1B,\n\tMODE_SYSTEM = 0x1F\n}\n\nexport enum ARMRegs {\n\tSP = 13,\n\tLR = 14,\n\tPC = 15,\n}\n\nexport enum ARMConstants {\n\n\tBANK_NONE = 0,\n\tBANK_FIQ = 1,\n\tBANK_IRQ = 2,\n\tBANK_SUPERVISOR = 3,\n\tBANK_ABORT = 4,\n\tBANK_UNDEFINED = 5,\n\n\tWORD_SIZE_ARM = 4,\n\tWORD_SIZE_THUMB = 2,\n\n\tBASE_RESET = 0x00000000,\n\tBASE_UNDEF = 0x00000004,\n\tBASE_SWI = 0x00000008,\n\tBASE_PABT = 0x0000000C,\n\tBASE_DABT = 0x00000010,\n\tBASE_IRQ = 0x00000018,\n\tBASE_FIQ = 0x0000001C,\n}\n\nconst UNALLOC_MASK = 0x0FFFFF00;\nconst USER_MASK = 0xF0000000;\nconst PRIV_MASK = 0x000000DF; // This is out of spec? (SEH)\nconst STATE_MASK = 0x00000020;\n\n\n///////////////////////////////////////////////////////////////////////////\n\nfunction ARMCoreArm(cpu: ARMCoreType) {\n\tthis.cpu = cpu;\n\n\tthis.addressingMode23Immediate = [\n\t\t// 000x0\n\t\tfunction(rn, offset, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn];\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] -= offset;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\t// 000xW\n\t\tnull,\n\n\t\tnull,\n\t\tnull,\n\n\t\t// 00Ux0\n\t\tfunction(rn, offset, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn];\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] += offset;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\t// 00UxW\n\t\tnull,\n\n\t\tnull,\n\t\tnull,\n\n\t\t// 0P0x0\n\t\tfunction(rn, offset, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\treturn /* addr = */ gprs[rn] - offset;\n\t\t\t};\n\t\t\taddress.writesPC = false;\n\t\t\treturn address;\n\t\t},\n\n\t\t// 0P0xW\n\t\tfunction(rn, offset, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn] - offset;\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] = addr;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\tnull,\n\t\tnull,\n\n\t\t// 0PUx0\n\t\tfunction(rn, offset, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\treturn /* addr = */ gprs[rn] + offset;\n\t\t\t};\n\t\t\taddress.writesPC = false;\n\t\t\treturn address;\n\t\t},\n\n\t\t// 0PUxW\n\t\tfunction(rn, offset, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn] + offset;\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] = addr;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\tnull,\n\t\tnull,\n\t];\n\n\tthis.addressingMode23Register = [\n\t\t// I00x0\n\t\tfunction(rn, rm, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn];\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] -= gprs[rm];\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\t// I00xW\n\t\tnull,\n\n\t\tnull,\n\t\tnull,\n\n\t\t// I0Ux0\n\t\tfunction(rn, rm, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn];\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] += gprs[rm];\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\t// I0UxW\n\t\tnull,\n\n\t\tnull,\n\t\tnull,\n\n\t\t// IP0x0\n\t\tfunction(rn, rm, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\treturn gprs[rn] - gprs[rm];\n\t\t\t};\n\t\t\taddress.writesPC = false;\n\t\t\treturn address;\n\t\t},\n\n\t\t// IP0xW\n\t\tfunction(rn, rm, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn] - gprs[rm];\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] = addr;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\tnull,\n\t\tnull,\n\n\t\t// IPUx0\n\t\tfunction(rn, rm, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn] + gprs[rm];\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = false;\n\t\t\treturn address;\n\t\t},\n\n\t\t// IPUxW\n\t\tfunction(rn, rm, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn] + gprs[rm];\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] = addr;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\tnull,\n\t\tnull\n\t];\n\n\tthis.addressingMode2RegisterShifted = [\n\t\t// I00x0\n\t\tfunction(rn, shiftOp, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn];\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tshiftOp();\n\t\t\t\t\tgprs[rn] -= cpu.shifterOperand;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\t// I00xW\n\t\tnull,\n\n\t\tnull,\n\t\tnull,\n\n\t\t// I0Ux0\n\t\tfunction(rn, shiftOp, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tvar addr = gprs[rn];\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tshiftOp();\n\t\t\t\t\tgprs[rn] += cpu.shifterOperand;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\t\t// I0UxW\n\t\tnull,\n\n\t\tnull,\n\t\tnull,\n\n\t\t// IP0x0\n\t\tfunction(rn, shiftOp, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tshiftOp();\n\t\t\t\treturn gprs[rn] - cpu.shifterOperand;\n\t\t\t};\n\t\t\taddress.writesPC = false;\n\t\t\treturn address;\n\t\t},\n\n\t\t// IP0xW\n\t\tfunction(rn, shiftOp, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tshiftOp();\n\t\t\t\tvar addr = gprs[rn] - cpu.shifterOperand;\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] = addr;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\tnull,\n\t\tnull,\n\n\t\t// IPUx0\n\t\tfunction(rn, shiftOp, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tshiftOp();\n\t\t\t\treturn gprs[rn] + cpu.shifterOperand;\n\t\t\t};\n\t\t\taddress.writesPC = false;\n\t\t\treturn address;\n\t\t},\n\n\t\t// IPUxW\n\t\tfunction(rn, shiftOp, condOp) {\n\t\t\tvar gprs = cpu.gprs;\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tshiftOp();\n\t\t\t\tvar addr = gprs[rn] + cpu.shifterOperand;\n\t\t\t\tif (!condOp || condOp()) {\n\t\t\t\t\tgprs[rn] = addr;\n\t\t\t\t}\n\t\t\t\treturn addr;\n\t\t\t};\n\t\t\taddress.writesPC = rn == ARMRegs.PC;\n\t\t\treturn address;\n\t\t},\n\n\t\tnull,\n\t\tnull,\n\t];\n}\n\nARMCoreArm.prototype.constructAddressingMode1ASR = function(rs, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\t++cpu.cycles;\n\t\tvar shift = gprs[rs];\n\t\tif (rs == ARMRegs.PC) {\n\t\t\tshift += 4;\n\t\t}\n\t\tshift &= 0xFF;\n\t\tvar shiftVal = gprs[rm];\n\t\tif (rm == ARMRegs.PC) {\n\t\t\tshiftVal += 4;\n\t\t}\n\t\tif (shift == 0) {\n\t\t\tcpu.shifterOperand = shiftVal;\n\t\t\tcpu.shifterCarryOut = cpu.cpsrC;\n\t\t} else if (shift < 32) {\n\t\t\tcpu.shifterOperand = shiftVal >> shift;\n\t\t\tcpu.shifterCarryOut = shiftVal & (1 << (shift - 1));\n\t\t} else if (gprs[rm] >> 31) {\n\t\t\tcpu.shifterOperand = 0xFFFFFFFF;\n\t\t\tcpu.shifterCarryOut = 0x80000000;\n\t\t} else {\n\t\t\tcpu.shifterOperand = 0;\n\t\t\tcpu.shifterCarryOut = 0;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructAddressingMode1Immediate = function(immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\treturn function() {\n\t\tcpu.shifterOperand = immediate;\n\t\tcpu.shifterCarryOut = cpu.cpsrC;\n\t};\n};\n\nARMCoreArm.prototype.constructAddressingMode1ImmediateRotate = function(immediate, rotate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\treturn function() {\n\t\tcpu.shifterOperand = (immediate >>> rotate) | (immediate << (32 - rotate));\n\t\tcpu.shifterCarryOut = cpu.shifterOperand >> 31;\n\t}\n};\n\nARMCoreArm.prototype.constructAddressingMode1LSL = function(rs, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\t++cpu.cycles;\n\t\tvar shift = gprs[rs];\n\t\tif (rs == ARMRegs.PC) {\n\t\t\tshift += 4;\n\t\t}\n\t\tshift &= 0xFF;\n\t\tvar shiftVal = gprs[rm];\n\t\tif (rm == ARMRegs.PC) {\n\t\t\tshiftVal += 4;\n\t\t}\n\t\tif (shift == 0) {\n\t\t\tcpu.shifterOperand = shiftVal;\n\t\t\tcpu.shifterCarryOut = cpu.cpsrC;\n\t\t} else if (shift < 32) {\n\t\t\tcpu.shifterOperand = shiftVal << shift;\n\t\t\tcpu.shifterCarryOut = shiftVal & (1 << (32 - shift));\n\t\t} else if (shift == 32) {\n\t\t\tcpu.shifterOperand = 0;\n\t\t\tcpu.shifterCarryOut = shiftVal & 1;\n\t\t} else {\n\t\t\tcpu.shifterOperand = 0;\n\t\t\tcpu.shifterCarryOut = 0;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructAddressingMode1LSR = function(rs, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\t++cpu.cycles;\n\t\tvar shift = gprs[rs];\n\t\tif (rs == ARMRegs.PC) {\n\t\t\tshift += 4;\n\t\t}\n\t\tshift &= 0xFF;\n\t\tvar shiftVal = gprs[rm];\n\t\tif (rm == ARMRegs.PC) {\n\t\t\tshiftVal += 4;\n\t\t}\n\t\tif (shift == 0) {\n\t\t\tcpu.shifterOperand = shiftVal;\n\t\t\tcpu.shifterCarryOut = cpu.cpsrC;\n\t\t} else if (shift < 32) {\n\t\t\tcpu.shifterOperand = shiftVal >>> shift;\n\t\t\tcpu.shifterCarryOut = shiftVal & (1 << (shift - 1));\n\t\t} else if (shift == 32) {\n\t\t\tcpu.shifterOperand = 0;\n\t\t\tcpu.shifterCarryOut = shiftVal >> 31;\n\t\t} else {\n\t\t\tcpu.shifterOperand = 0;\n\t\t\tcpu.shifterCarryOut = 0;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructAddressingMode1ROR = function(rs, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\t++cpu.cycles;\n\t\tvar shift = gprs[rs];\n\t\tif (rs == ARMRegs.PC) {\n\t\t\tshift += 4;\n\t\t}\n\t\tshift &= 0xFF;\n\t\tvar shiftVal = gprs[rm];\n\t\tif (rm == ARMRegs.PC) {\n\t\t\tshiftVal += 4;\n\t\t}\n\t\tvar rotate = shift & 0x1F;\n\t\tif (shift == 0) {\n\t\t\tcpu.shifterOperand = shiftVal;\n\t\t\tcpu.shifterCarryOut = cpu.cpsrC;\n\t\t} else if (rotate) {\n\t\t\tcpu.shifterOperand = (gprs[rm] >>> rotate) | (gprs[rm] << (32 - rotate));\n\t\t\tcpu.shifterCarryOut = shiftVal & (1 << (rotate - 1));\n\t\t} else {\n\t\t\tcpu.shifterOperand = shiftVal;\n\t\t\tcpu.shifterCarryOut = shiftVal >> 31;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructAddressingMode23Immediate = function(instruction, immediate, condOp) {\n\tvar rn = (instruction & 0x000F0000) >> 16;\n\treturn this.addressingMode23Immediate[(instruction & 0x01A00000) >> 21](rn, immediate, condOp);\n};\n\nARMCoreArm.prototype.constructAddressingMode23Register = function(instruction, rm, condOp) {\n\tvar rn = (instruction & 0x000F0000) >> 16;\n\treturn this.addressingMode23Register[(instruction & 0x01A00000) >> 21](rn, rm, condOp);\n};\n\nARMCoreArm.prototype.constructAddressingMode2RegisterShifted = function(instruction, shiftOp, condOp) {\n\tvar rn = (instruction & 0x000F0000) >> 16;\n\treturn this.addressingMode2RegisterShifted[(instruction & 0x01A00000) >> 21](rn, shiftOp, condOp);\n};\n\nARMCoreArm.prototype.constructAddressingMode4 = function(immediate, rn) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tvar addr = gprs[rn] + immediate;\n\t\treturn addr;\n\t}\n};\n\nARMCoreArm.prototype.constructAddressingMode4Writeback = function(immediate, offset, rn, overlap) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function(writeInitial) {\n\t\tvar addr = gprs[rn] + immediate;\n\t\tif (writeInitial && overlap) {\n\t\t\tcpu.mmu.store32(gprs[rn] + immediate - 4, gprs[rn]);\n\t\t}\n\t\tgprs[rn] += offset;\n\t\treturn addr;\n\t}\n};\n\nARMCoreArm.prototype.constructADC = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar shifterOperand = (cpu.shifterOperand >>> 0) + (cpu.cpsrC ? 1 : 0);\n\t\tgprs[rd] = (gprs[rn] >>> 0) + shifterOperand;\n\t};\n};\n\nARMCoreArm.prototype.constructADCS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar shifterOperand = (cpu.shifterOperand >>> 0) + (cpu.cpsrC ? 1 : 0);\n\t\tvar d = (gprs[rn] >>> 0) + shifterOperand;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = d >> 31;\n\t\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = d > 0xFFFFFFFF;\n\t\t\tcpu.cpsrV = (gprs[rn] >> 31) == (shifterOperand >> 31) &&\n\t\t\t\t\t\t(gprs[rn] >> 31) != (d >> 31) &&\n\t\t\t\t\t\t(shifterOperand >> 31) != (d >> 31);\n\t\t}\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreArm.prototype.constructADD = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = (gprs[rn] >>> 0) + (cpu.shifterOperand >>> 0);\n\t};\n};\n\nARMCoreArm.prototype.constructADDS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar d = (gprs[rn] >>> 0) + (cpu.shifterOperand >>> 0);\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = d >> 31;\n\t\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = d > 0xFFFFFFFF;\n\t\t\tcpu.cpsrV = (gprs[rn] >> 31) == (cpu.shifterOperand >> 31) &&\n\t\t\t\t\t\t(gprs[rn] >> 31) != (d >> 31) &&\n\t\t\t\t\t\t(cpu.shifterOperand >> 31) != (d >> 31);\n\t\t}\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreArm.prototype.constructAND = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = gprs[rn] & cpu.shifterOperand;\n\t};\n};\n\nARMCoreArm.prototype.constructANDS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = gprs[rn] & cpu.shifterOperand;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = cpu.shifterCarryOut;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructB = function(immediate, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tif (condOp && !condOp()) {\n\t\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\t\treturn;\n\t\t}\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tgprs[ARMRegs.PC] += immediate;\n\t};\n};\n\nARMCoreArm.prototype.constructBIC = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = gprs[rn] & ~cpu.shifterOperand;\n\t};\n};\n\nARMCoreArm.prototype.constructBICS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = gprs[rn] & ~cpu.shifterOperand;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = cpu.shifterCarryOut;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructBL = function(immediate, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tif (condOp && !condOp()) {\n\t\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\t\treturn;\n\t\t}\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tgprs[ARMRegs.LR] = gprs[ARMRegs.PC] - 4;\n\t\tgprs[ARMRegs.PC] += immediate;\n\t};\n};\n\nARMCoreArm.prototype.constructBX = function(rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tif (condOp && !condOp()) {\n\t\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\t\treturn;\n\t\t}\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tcpu.switchExecMode(gprs[rm] & 0x00000001);\n\t\tgprs[ARMRegs.PC] = gprs[rm] & 0xFFFFFFFE;\n\t};\n};\n\nARMCoreArm.prototype.constructCMN = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar aluOut = (gprs[rn] >>> 0) + (cpu.shifterOperand >>> 0);\n\t\tcpu.cpsrN = aluOut >> 31;\n\t\tcpu.cpsrZ = !(aluOut & 0xFFFFFFFF);\n\t\tcpu.cpsrC = aluOut > 0xFFFFFFFF;\n\t\tcpu.cpsrV = (gprs[rn] >> 31) == (cpu.shifterOperand >> 31) &&\n\t\t\t\t\t(gprs[rn] >> 31) != (aluOut >> 31) &&\n\t\t\t\t\t(cpu.shifterOperand >> 31) != (aluOut >> 31);\n\t};\n};\n\nARMCoreArm.prototype.constructCMP = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar aluOut = gprs[rn] - cpu.shifterOperand;\n\t\tcpu.cpsrN = aluOut >> 31;\n\t\tcpu.cpsrZ = !(aluOut & 0xFFFFFFFF);\n\t\tcpu.cpsrC = (gprs[rn] >>> 0) >= (cpu.shifterOperand >>> 0);\n\t\tcpu.cpsrV = (gprs[rn] >> 31) != (cpu.shifterOperand >> 31) &&\n\t\t\t\t\t(gprs[rn] >> 31) != (aluOut >> 31);\n\t};\n};\n\nARMCoreArm.prototype.constructEOR = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = gprs[rn] ^ cpu.shifterOperand;\n\t};\n};\n\nARMCoreArm.prototype.constructEORS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = gprs[rn] ^ cpu.shifterOperand;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = cpu.shifterCarryOut;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructLDM = function(rs, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\tvar mmu = cpu.mmu;\n\treturn function() {\n\t\tmmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address(false);\n\t\tvar total = 0;\n\t\tvar m, i;\n\t\tfor (m = rs, i = 0; m; m >>= 1, ++i) {\n\t\t\tif (m & 1) {\n\t\t\t\tgprs[i] = mmu.load32(addr & 0xFFFFFFFC);\n\t\t\t\taddr += 4;\n\t\t\t\t++total;\n\t\t\t}\n\t\t}\n\t\tmmu.waitMulti32(addr, total);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreArm.prototype.constructLDMS = function(rs, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\tvar mmu = cpu.mmu;\n\treturn function() {\n\t\tmmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address(false);\n\t\tvar total = 0;\n\t\tvar mode = cpu.mode;\n\t\tcpu.switchMode(ARMMode.MODE_SYSTEM);\n\t\tvar m, i;\n\t\tfor (m = rs, i = 0; m; m >>= 1, ++i) {\n\t\t\tif (m & 1) {\n\t\t\t\tgprs[i] = mmu.load32(addr & 0xFFFFFFFC);\n\t\t\t\taddr += 4;\n\t\t\t\t++total;\n\t\t\t}\n\t\t}\n\t\tcpu.switchMode(mode);\n\t\tmmu.waitMulti32(addr, total);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreArm.prototype.constructLDR = function(rd, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address();\n\t\tgprs[rd] = cpu.mmu.load32(addr);\n\t\tcpu.mmu.wait32(addr);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreArm.prototype.constructLDRB = function(rd, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address();\n\t\tgprs[rd] = cpu.mmu.loadU8(addr);\n\t\tcpu.mmu.wait(addr);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreArm.prototype.constructLDRH = function(rd, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address();\n\t\tgprs[rd] = cpu.mmu.loadU16(addr);\n\t\tcpu.mmu.wait(addr);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreArm.prototype.constructLDRSB = function(rd, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address();\n\t\tgprs[rd] = cpu.mmu.load8(addr);\n\t\tcpu.mmu.wait(addr);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreArm.prototype.constructLDRSH = function(rd, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address();\n\t\tgprs[rd] = cpu.mmu.load16(addr);\n\t\tcpu.mmu.wait(addr);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreArm.prototype.constructMLA = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\t++cpu.cycles;\n\t\tcpu.mmu.waitMul(rs);\n\t\tif ((gprs[rm] & 0xFFFF0000) && (gprs[rs] & 0xFFFF0000)) {\n\t\t\t// Our data type is a double--we'll lose bits if we do it all at once!\n\t\t\tvar hi = ((gprs[rm] & 0xFFFF0000) * gprs[rs]) & 0xFFFFFFFF;\n\t\t\tvar lo = ((gprs[rm] & 0x0000FFFF) * gprs[rs]) & 0xFFFFFFFF;\n\t\t\tgprs[rd] = (hi + lo + gprs[rn]) & 0xFFFFFFFF;\n\t\t} else {\n\t\t\tgprs[rd] = gprs[rm] * gprs[rs] + gprs[rn];\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructMLAS = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\t++cpu.cycles;\n\t\tcpu.mmu.waitMul(rs);\n\t\tif ((gprs[rm] & 0xFFFF0000) && (gprs[rs] & 0xFFFF0000)) {\n\t\t\t// Our data type is a double--we'll lose bits if we do it all at once!\n\t\t\tvar hi = ((gprs[rm] & 0xFFFF0000) * gprs[rs]) & 0xFFFFFFFF;\n\t\t\tvar lo = ((gprs[rm] & 0x0000FFFF) * gprs[rs]) & 0xFFFFFFFF;\n\t\t\tgprs[rd] = (hi + lo + gprs[rn]) & 0xFFFFFFFF;\n\t\t} else {\n\t\t\tgprs[rd] = gprs[rm] * gprs[rs] + gprs[rn];\n\t\t}\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreArm.prototype.constructMOV = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = cpu.shifterOperand;\n\t};\n};\n\nARMCoreArm.prototype.constructMOVS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = cpu.shifterOperand;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = cpu.shifterCarryOut;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructMRS = function(rd, r, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tif (r) {\n\t\t\tgprs[rd] = cpu.spsr;\n\t\t} else {\n\t\t\tgprs[rd] = cpu.packCPSR();\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructMSR = function(rm, r, instruction, immediate, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\tvar c = instruction & 0x00010000;\n\t//var x = instruction & 0x00020000;\n\t//var s = instruction & 0x00040000;\n\tvar f = instruction & 0x00080000;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tvar operand;\n\t\tif (instruction & 0x02000000) {\n\t\t\toperand = immediate;\n\t\t} else {\n\t\t\toperand = gprs[rm];\n\t\t}\n\t\tvar mask = (c ? 0x000000FF : 0x00000000) |\n\t\t\t\t //(x ? 0x0000FF00 : 0x00000000) | // Irrelevant on ARMv4T\n\t\t\t\t //(s ? 0x00FF0000 : 0x00000000) | // Irrelevant on ARMv4T\n\t\t\t\t (f ? 0xFF000000 : 0x00000000);\n\t\tif (r) {\n\t\t\tmask &= USER_MASK | PRIV_MASK | STATE_MASK;\n\t\t\t//console.log(hex(r), hex(mask & 0x7fffffff), hex(cpu.spsr), hex(operand));\n\t\t\tcpu.spsr = (cpu.spsr & ~mask) | (operand & mask);\n\t\t} else {\n\t\t\tif (mask & USER_MASK) {\n\t\t\t\tcpu.cpsrN = operand >> 31;\n\t\t\t\tcpu.cpsrZ = operand & 0x40000000;\n\t\t\t\tcpu.cpsrC = operand & 0x20000000;\n\t\t\t\tcpu.cpsrV = operand & 0x10000000;\n\t\t\t}\n\t\t\tif (cpu.mode != ARMMode.MODE_USER && (mask & PRIV_MASK)) {\n\t\t\t\tcpu.switchMode((operand & 0x0000000F) | 0x00000010);\n\t\t\t\tcpu.cpsrI = operand & 0x00000080;\n\t\t\t\tcpu.cpsrF = operand & 0x00000040;\n\t\t\t}\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructMUL = function(rd, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tcpu.mmu.waitMul(gprs[rs]);\n\t\tif ((gprs[rm] & 0xFFFF0000) && (gprs[rs] & 0xFFFF0000)) {\n\t\t\t// Our data type is a double--we'll lose bits if we do it all at once!\n\t\t\tvar hi = ((gprs[rm] & 0xFFFF0000) * gprs[rs]) | 0;\n\t\t\tvar lo = ((gprs[rm] & 0x0000FFFF) * gprs[rs]) | 0;\n\t\t\tgprs[rd] = hi + lo;\n\t\t} else {\n\t\t\tgprs[rd] = gprs[rm] * gprs[rs];\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructMULS = function(rd, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tcpu.mmu.waitMul(gprs[rs]);\n\t\tif ((gprs[rm] & 0xFFFF0000) && (gprs[rs] & 0xFFFF0000)) {\n\t\t\t// Our data type is a double--we'll lose bits if we do it all at once!\n\t\t\tvar hi = ((gprs[rm] & 0xFFFF0000) * gprs[rs]) | 0;\n\t\t\tvar lo = ((gprs[rm] & 0x0000FFFF) * gprs[rs]) | 0;\n\t\t\tgprs[rd] = hi + lo;\n\t\t} else {\n\t\t\tgprs[rd] = gprs[rm] * gprs[rs];\n\t\t}\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreArm.prototype.constructMVN = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = ~cpu.shifterOperand;\n\t};\n};\n\nARMCoreArm.prototype.constructMVNS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = ~cpu.shifterOperand;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = cpu.shifterCarryOut;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructORR = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = gprs[rn] | cpu.shifterOperand;\n\t}\n};\n\nARMCoreArm.prototype.constructORRS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = gprs[rn] | cpu.shifterOperand;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = cpu.shifterCarryOut;\n\t\t}\n\t};\n};\n\nARMCoreArm.prototype.constructRSB = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = cpu.shifterOperand - gprs[rn];\n\t};\n};\n\nARMCoreArm.prototype.constructRSBS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar d = cpu.shifterOperand - gprs[rn];\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = d >> 31;\n\t\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = (cpu.shifterOperand >>> 0) >= (gprs[rn] >>> 0);\n\t\t\tcpu.cpsrV = (cpu.shifterOperand >> 31) != (gprs[rn] >> 31) &&\n\t\t\t\t\t\t(cpu.shifterOperand >> 31) != (d >> 31);\n\t\t}\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreArm.prototype.constructRSC = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar n = (gprs[rn] >>> 0) + (cpu.cpsrC ? 0 : 1);\n\t\tgprs[rd] = (cpu.shifterOperand >>> 0) - n;\n\t};\n};\n\nARMCoreArm.prototype.constructRSCS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar n = (gprs[rn] >>> 0) + (cpu.cpsrC ? 0 : 1);\n\t\tvar d = (cpu.shifterOperand >>> 0) - n;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = d >> 31;\n\t\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = (cpu.shifterOperand >>> 0) >= (d >>> 0);\n\t\t\tcpu.cpsrV = (cpu.shifterOperand >> 31) != (n >> 31) &&\n\t\t\t\t\t\t(cpu.shifterOperand >> 31) != (d >> 31);\n\t\t}\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreArm.prototype.constructSBC = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar shifterOperand = (cpu.shifterOperand >>> 0) + (cpu.cpsrC ? 0 : 1);\n\t\tgprs[rd] = (gprs[rn] >>> 0) - shifterOperand;\n\t};\n};\n\nARMCoreArm.prototype.constructSBCS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar shifterOperand = (cpu.shifterOperand >>> 0) + (cpu.cpsrC ? 0 : 1);\n\t\tvar d = (gprs[rn] >>> 0) - shifterOperand;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = d >> 31;\n\t\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = (gprs[rn] >>> 0) >= (d >>> 0);\n\t\t\tcpu.cpsrV = (gprs[rn] >> 31) != (shifterOperand >> 31) &&\n\t\t\t\t\t\t(gprs[rn] >> 31) != (d >> 31);\n\t\t}\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreArm.prototype.constructSMLAL = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar SHIFT_32 = 1/0x100000000;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tcpu.cycles += 2;\n\t\tcpu.mmu.waitMul(rs);\n\t\tvar hi = (gprs[rm] & 0xFFFF0000) * gprs[rs];\n\t\tvar lo = (gprs[rm] & 0x0000FFFF) * gprs[rs];\n\t\tvar carry = (gprs[rn] >>> 0) + hi + lo;\n\t\tgprs[rn] = carry;\n\t\tgprs[rd] += Math.floor(carry * SHIFT_32);\n\t};\n};\n\nARMCoreArm.prototype.constructSMLALS = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar SHIFT_32 = 1/0x100000000;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tcpu.cycles += 2;\n\t\tcpu.mmu.waitMul(rs);\n\t\tvar hi = (gprs[rm] & 0xFFFF0000) * gprs[rs];\n\t\tvar lo = (gprs[rm] & 0x0000FFFF) * gprs[rs];\n\t\tvar carry = (gprs[rn] >>> 0) + hi + lo;\n\t\tgprs[rn] = carry;\n\t\tgprs[rd] += Math.floor(carry * SHIFT_32);\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !((gprs[rd] & 0xFFFFFFFF) || (gprs[rn] & 0xFFFFFFFF));\n\t};\n};\n\nARMCoreArm.prototype.constructSMULL = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar SHIFT_32 = 1/0x100000000;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\t++cpu.cycles;\n\t\tcpu.mmu.waitMul(gprs[rs]);\n\t\tvar hi = ((gprs[rm] & 0xFFFF0000) >> 0) * (gprs[rs] >> 0);\n\t\tvar lo = ((gprs[rm] & 0x0000FFFF) >> 0) * (gprs[rs] >> 0);\n\t\tgprs[rn] = ((hi & 0xFFFFFFFF) + (lo & 0xFFFFFFFF)) & 0xFFFFFFFF;\n\t\tgprs[rd] = Math.floor(hi * SHIFT_32 + lo * SHIFT_32);\n\t};\n};\n\nARMCoreArm.prototype.constructSMULLS = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar SHIFT_32 = 1/0x100000000;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\t++cpu.cycles;\n\t\tcpu.mmu.waitMul(gprs[rs]);\n\t\tvar hi = ((gprs[rm] & 0xFFFF0000) >> 0) * (gprs[rs] >> 0);\n\t\tvar lo = ((gprs[rm] & 0x0000FFFF) >> 0) * (gprs[rs] >> 0);\n\t\tgprs[rn] = ((hi & 0xFFFFFFFF) + (lo & 0xFFFFFFFF)) & 0xFFFFFFFF;\n\t\tgprs[rd] = Math.floor(hi * SHIFT_32 + lo * SHIFT_32);\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !((gprs[rd] & 0xFFFFFFFF) || (gprs[rn] & 0xFFFFFFFF));\n\t};\n};\n\nARMCoreArm.prototype.constructSTM = function(rs, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\tvar mmu = cpu.mmu;\n\treturn function() {\n\t\tif (condOp && !condOp()) {\n\t\t\tmmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\t\treturn;\n\t\t}\n\t\tmmu.wait32(gprs[ARMRegs.PC]);\n\t\tvar addr = address(true);\n\t\tvar total = 0;\n\t\tvar m, i;\n\t\tfor (m = rs, i = 0; m; m >>= 1, ++i) {\n\t\t\tif (m & 1) {\n\t\t\t\tmmu.store32(addr, gprs[i]);\n\t\t\t\taddr += 4;\n\t\t\t\t++total;\n\t\t\t}\n\t\t}\n\t\tmmu.waitMulti32(addr, total);\n\t};\n};\n\nARMCoreArm.prototype.constructSTMS = function(rs, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\tvar mmu = cpu.mmu;\n\treturn function() {\n\t\tif (condOp && !condOp()) {\n\t\t\tmmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\t\treturn;\n\t\t}\n\t\tmmu.wait32(gprs[ARMRegs.PC]);\n\t\tvar mode = cpu.mode;\n\t\tvar addr = address(true);\n\t\tvar total = 0;\n\t\tvar m, i;\n\t\tcpu.switchMode(ARMMode.MODE_SYSTEM);\n\t\tfor (m = rs, i = 0; m; m >>= 1, ++i) {\n\t\t\tif (m & 1) {\n\t\t\t\tmmu.store32(addr, gprs[i]);\n\t\t\t\taddr += 4;\n\t\t\t\t++total;\n\t\t\t}\n\t\t}\n\t\tcpu.switchMode(mode);\n\t\tmmu.waitMulti32(addr, total);\n\t};\n};\n\nARMCoreArm.prototype.constructSTR = function(rd, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tif (condOp && !condOp()) {\n\t\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address();\n\t\tcpu.mmu.store32(addr, gprs[rd]);\n\t\tcpu.mmu.wait32(addr);\n\t\tcpu.mmu.wait32(gprs[ARMRegs.PC]);\n\t};\n};\n\nARMCoreArm.prototype.constructSTRB = function(rd, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tif (condOp && !condOp()) {\n\t\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address();\n\t\tcpu.mmu.store8(addr, gprs[rd]);\n\t\tcpu.mmu.wait(addr);\n\t\tcpu.mmu.wait32(gprs[ARMRegs.PC]);\n\t};\n};\n\nARMCoreArm.prototype.constructSTRH = function(rd, address, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tif (condOp && !condOp()) {\n\t\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\t\treturn;\n\t\t}\n\t\tvar addr = address();\n\t\tcpu.mmu.store16(addr, gprs[rd]);\n\t\tcpu.mmu.wait(addr);\n\t\tcpu.mmu.wait32(gprs[ARMRegs.PC]);\n\t};\n};\n\nARMCoreArm.prototype.constructSUB = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tgprs[rd] = gprs[rn] - cpu.shifterOperand;\n\t};\n};\n\nARMCoreArm.prototype.constructSUBS = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar d = gprs[rn] - cpu.shifterOperand;\n\t\tif (rd == ARMRegs.PC && cpu.hasSPSR()) {\n\t\t\tcpu.unpackCPSR(cpu.spsr);\n\t\t} else {\n\t\t\tcpu.cpsrN = d >> 31;\n\t\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\t\tcpu.cpsrC = (gprs[rn] >>> 0) >= (cpu.shifterOperand >>> 0);\n\t\t\tcpu.cpsrV = (gprs[rn] >> 31) != (cpu.shifterOperand >> 31) &&\n\t\t\t\t\t\t(gprs[rn] >> 31) != (d >> 31);\n\t\t}\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreArm.prototype.constructSWI = function(immediate, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tif (condOp && !condOp()) {\n\t\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\t\treturn;\n\t\t}\n\t\tcpu.irq.swi32(immediate);\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t};\n};\n\nARMCoreArm.prototype.constructSWP = function(rd, rn, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tcpu.mmu.wait32(gprs[rn]);\n\t\tcpu.mmu.wait32(gprs[rn]);\n\t\tvar d = cpu.mmu.load32(gprs[rn]);\n\t\tcpu.mmu.store32(gprs[rn], gprs[rm]);\n\t\tgprs[rd] = d;\n\t\t++cpu.cycles;\n\t}\n};\n\nARMCoreArm.prototype.constructSWPB = function(rd, rn, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tcpu.mmu.wait(gprs[rn]);\n\t\tcpu.mmu.wait(gprs[rn]);\n\t\tvar d = cpu.mmu.loadU8(gprs[rn]);\n\t\tcpu.mmu.store8(gprs[rn], gprs[rm]);\n\t\tgprs[rd] = d;\n\t\t++cpu.cycles;\n\t}\n};\n\nARMCoreArm.prototype.constructTEQ = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar aluOut = gprs[rn] ^ cpu.shifterOperand;\n\t\tcpu.cpsrN = aluOut >> 31;\n\t\tcpu.cpsrZ = !(aluOut & 0xFFFFFFFF);\n\t\tcpu.cpsrC = cpu.shifterCarryOut;\n\t};\n};\n\nARMCoreArm.prototype.constructTST = function(rd, rn, shiftOp, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tshiftOp();\n\t\tvar aluOut = gprs[rn] & cpu.shifterOperand;\n\t\tcpu.cpsrN = aluOut >> 31;\n\t\tcpu.cpsrZ = !(aluOut & 0xFFFFFFFF);\n\t\tcpu.cpsrC = cpu.shifterCarryOut;\n\t};\n};\n\nARMCoreArm.prototype.constructUMLAL = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar SHIFT_32 = 1/0x100000000;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tcpu.cycles += 2;\n\t\tcpu.mmu.waitMul(rs);\n\t\tvar hi = ((gprs[rm] & 0xFFFF0000) >>> 0) * (gprs[rs] >>> 0);\n\t\tvar lo = (gprs[rm] & 0x0000FFFF) * (gprs[rs] >>> 0);\n\t\tvar carry = (gprs[rn] >>> 0) + hi + lo;\n\t\tgprs[rn] = carry;\n\t\tgprs[rd] += carry * SHIFT_32;\n\t};\n};\n\nARMCoreArm.prototype.constructUMLALS = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar SHIFT_32 = 1/0x100000000;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\tcpu.cycles += 2;\n\t\tcpu.mmu.waitMul(rs);\n\t\tvar hi = ((gprs[rm] & 0xFFFF0000) >>> 0) * (gprs[rs] >>> 0);\n\t\tvar lo = (gprs[rm] & 0x0000FFFF) * (gprs[rs] >>> 0);\n\t\tvar carry = (gprs[rn] >>> 0) + hi + lo;\n\t\tgprs[rn] = carry;\n\t\tgprs[rd] += carry * SHIFT_32;\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !((gprs[rd] & 0xFFFFFFFF) || (gprs[rn] & 0xFFFFFFFF));\n\t};\n};\n\nARMCoreArm.prototype.constructUMULL = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar SHIFT_32 = 1/0x100000000;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\t++cpu.cycles;\n\t\tcpu.mmu.waitMul(gprs[rs]);\n\t\tvar hi = ((gprs[rm] & 0xFFFF0000) >>> 0) * (gprs[rs] >>> 0);\n\t\tvar lo = ((gprs[rm] & 0x0000FFFF) >>> 0) * (gprs[rs] >>> 0);\n\t\tgprs[rn] = ((hi & 0xFFFFFFFF) + (lo & 0xFFFFFFFF)) & 0xFFFFFFFF;\n\t\tgprs[rd] = (hi * SHIFT_32 + lo * SHIFT_32) >>> 0;\n\t};\n};\n\nARMCoreArm.prototype.constructUMULLS = function(rd, rn, rs, rm, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar SHIFT_32 = 1/0x100000000;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch32(gprs[ARMRegs.PC]);\n\t\tif (condOp && !condOp()) {\n\t\t\treturn;\n\t\t}\n\t\t++cpu.cycles;\n\t\tcpu.mmu.waitMul(gprs[rs]);\n\t\tvar hi = ((gprs[rm] & 0xFFFF0000) >>> 0) * (gprs[rs] >>> 0);\n\t\tvar lo = ((gprs[rm] & 0x0000FFFF) >>> 0) * (gprs[rs] >>> 0);\n\t\tgprs[rn] = ((hi & 0xFFFFFFFF) + (lo & 0xFFFFFFFF)) & 0xFFFFFFFF;\n\t\tgprs[rd] = (hi * SHIFT_32 + lo * SHIFT_32) >>> 0;\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !((gprs[rd] & 0xFFFFFFFF) || (gprs[rn] & 0xFFFFFFFF));\n\t};\n};\n\n///////////////////////////////////////////////////////////////////////////\n\nfunction ARMCoreThumb(cpu) {\n\tthis.cpu = cpu;\n};\n\nARMCoreThumb.prototype.constructADC = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar m = (gprs[rm] >>> 0) + (cpu.cpsrC ? 1 : 0);\n\t\tvar oldD = gprs[rd];\n\t\tvar d = (oldD >>> 0) + m;\n\t\tvar oldDn = oldD >> 31;\n\t\tvar dn = d >> 31;\n\t\tvar mn = m >> 31;\n\t\tcpu.cpsrN = dn;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = d > 0xFFFFFFFF;\n\t\tcpu.cpsrV = oldDn == mn && oldDn != dn && mn != dn;\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreThumb.prototype.constructADD1 = function(rd, rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar d = (gprs[rn] >>> 0) + immediate;\n\t\tcpu.cpsrN = d >> 31;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = d > 0xFFFFFFFF;\n\t\tcpu.cpsrV = !(gprs[rn] >> 31) && ((gprs[rn] >> 31 ^ d) >> 31) && (d >> 31);\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreThumb.prototype.constructADD2 = function(rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar d = (gprs[rn] >>> 0) + immediate;\n\t\tcpu.cpsrN = d >> 31;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = d > 0xFFFFFFFF;\n\t\tcpu.cpsrV = !(gprs[rn] >> 31) && ((gprs[rn] ^ d) >> 31) && ((immediate ^ d) >> 31);\n\t\tgprs[rn] = d;\n\t};\n};\n\nARMCoreThumb.prototype.constructADD3 = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar d = (gprs[rn] >>> 0) + (gprs[rm] >>> 0);\n\t\tcpu.cpsrN = d >> 31;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = d > 0xFFFFFFFF;\n\t\tcpu.cpsrV = !((gprs[rn] ^ gprs[rm]) >> 31) && ((gprs[rn] ^ d) >> 31) && ((gprs[rm] ^ d) >> 31);\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreThumb.prototype.constructADD4 = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] += gprs[rm];\n\t};\n};\n\nARMCoreThumb.prototype.constructADD5 = function(rd, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = (gprs[ARMRegs.PC] & 0xFFFFFFFC) + immediate;\n\t};\n};\n\nARMCoreThumb.prototype.constructADD6 = function(rd, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = gprs[ARMRegs.SP] + immediate;\n\t};\n};\n\nARMCoreThumb.prototype.constructADD7 = function(immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[ARMRegs.SP] += immediate;\n\t};\n};\n\nARMCoreThumb.prototype.constructAND = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = gprs[rd] & gprs[rm];\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructASR1 = function(rd, rm, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tif (immediate == 0) {\n\t\t\tcpu.cpsrC = gprs[rm] >> 31;\n\t\t\tif (cpu.cpsrC) {\n\t\t\t\tgprs[rd] = 0xFFFFFFFF;\n\t\t\t} else {\n\t\t\t\tgprs[rd] = 0;\n\t\t\t}\n\t\t} else {\n\t\t\tcpu.cpsrC = gprs[rm] & (1 << (immediate - 1));\n\t\t\tgprs[rd] = gprs[rm] >> immediate;\n\t\t}\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructASR2 = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar rs = gprs[rm] & 0xFF;\n\t\tif (rs) {\n\t\t\tif (rs < 32) {\n\t\t\t\tcpu.cpsrC = gprs[rd] & (1 << (rs - 1));\n\t\t\t\tgprs[rd] >>= rs;\n\t\t\t} else {\n\t\t\t\tcpu.cpsrC = gprs[rd] >> 31;\n\t\t\t\tif (cpu.cpsrC) {\n\t\t\t\t\tgprs[rd] = 0xFFFFFFFF;\n\t\t\t\t} else {\n\t\t\t\t\tgprs[rd] = 0;\n\t\t\t\t}\n\t\t\t}\n\t\t}\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructB1 = function(immediate, condOp) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tif (condOp()) {\n\t\t\tgprs[ARMRegs.PC] += immediate;\n\t\t}\n\t};\n};\n\nARMCoreThumb.prototype.constructB2 = function(immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[ARMRegs.PC] += immediate;\n\t};\n};\n\nARMCoreThumb.prototype.constructBIC = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = gprs[rd] & ~gprs[rm];\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructBL1 = function(immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[ARMRegs.LR] = gprs[ARMRegs.PC] + immediate;\n\t}\n};\n\nARMCoreThumb.prototype.constructBL2 = function(immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar pc = gprs[ARMRegs.PC];\n\t\tgprs[ARMRegs.PC] = gprs[ARMRegs.LR] + (immediate << 1);\n\t\tgprs[ARMRegs.LR] = pc - 1;\n\t}\n};\n\nARMCoreThumb.prototype.constructBX = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tcpu.switchExecMode(gprs[rm] & 0x00000001);\n\t\tvar misalign = 0;\n\t\tif (rm == 15) {\n\t\t\tmisalign = gprs[rm] & 0x00000002;\n\t\t}\n\t\tgprs[ARMRegs.PC] = gprs[rm] & 0xFFFFFFFE - misalign;\n\t};\n};\n\nARMCoreThumb.prototype.constructCMN = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar aluOut = (gprs[rd] >>> 0) + (gprs[rm] >>> 0);\n\t\tcpu.cpsrN = aluOut >> 31;\n\t\tcpu.cpsrZ = !(aluOut & 0xFFFFFFFF);\n\t\tcpu.cpsrC = aluOut > 0xFFFFFFFF;\n\t\tcpu.cpsrV = (gprs[rd] >> 31) == (gprs[rm] >> 31) &&\n\t\t\t\t\t(gprs[rd] >> 31) != (aluOut >> 31) &&\n\t\t\t\t\t(gprs[rm] >> 31) != (aluOut >> 31);\n\t};\n};\n\nARMCoreThumb.prototype.constructCMP1 = function(rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar aluOut = gprs[rn] - immediate;\n\t\tcpu.cpsrN = aluOut >> 31;\n\t\tcpu.cpsrZ = !(aluOut & 0xFFFFFFFF);\n\t\tcpu.cpsrC = (gprs[rn] >>> 0) >= immediate;\n\t\tcpu.cpsrV = (gprs[rn] >> 31) && ((gprs[rn] ^ aluOut) >> 31);\n\t};\n}\n\nARMCoreThumb.prototype.constructCMP2 = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar d = gprs[rd];\n\t\tvar m = gprs[rm];\n\t\tvar aluOut = d - m;\n\t\tvar an = aluOut >> 31;\n\t\tvar dn = d >> 31;\n\t\tcpu.cpsrN = an;\n\t\tcpu.cpsrZ = !(aluOut & 0xFFFFFFFF);\n\t\tcpu.cpsrC = (d >>> 0) >= (m >>> 0);\n\t\tcpu.cpsrV = dn != (m >> 31) && dn != an;\n\t};\n};\n\nARMCoreThumb.prototype.constructCMP3 = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar aluOut = gprs[rd] - gprs[rm];\n\t\tcpu.cpsrN = aluOut >> 31;\n\t\tcpu.cpsrZ = !(aluOut & 0xFFFFFFFF);\n\t\tcpu.cpsrC = (gprs[rd] >>> 0) >= (gprs[rm] >>> 0);\n\t\tcpu.cpsrV = ((gprs[rd] ^ gprs[rm]) >> 31) && ((gprs[rd] ^ aluOut) >> 31);\n\t};\n};\n\nARMCoreThumb.prototype.constructEOR = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = gprs[rd] ^ gprs[rm];\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructLDMIA = function(rn, rs) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar address = gprs[rn];\n\t\tvar total = 0;\n\t\tvar m, i;\n\t\tfor (m = 0x01, i = 0; i < 8; m <<= 1, ++i) {\n\t\t\tif (rs & m) {\n\t\t\t\tgprs[i] = cpu.mmu.load32(address);\n\t\t\t\taddress += 4;\n\t\t\t\t++total;\n\t\t\t}\n\t\t}\n\t\tcpu.mmu.waitMulti32(address, total);\n\t\tif (!((1 << rn) & rs)) {\n\t\t\tgprs[rn] = address;\n\t\t}\n\t};\n};\n\nARMCoreThumb.prototype.constructLDR1 = function(rd, rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar n = gprs[rn] + immediate;\n\t\tgprs[rd] = cpu.mmu.load32(n);\n\t\tcpu.mmu.wait32(n);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreThumb.prototype.constructLDR2 = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = cpu.mmu.load32(gprs[rn] + gprs[rm]);\n\t\tcpu.mmu.wait32(gprs[rn] + gprs[rm]);\n\t\t++cpu.cycles;\n\t}\n};\n\nARMCoreThumb.prototype.constructLDR3 = function(rd, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = cpu.mmu.load32((gprs[ARMRegs.PC] & 0xFFFFFFFC) + immediate);\n\t\tcpu.mmu.wait32(gprs[ARMRegs.PC]);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreThumb.prototype.constructLDR4 = function(rd, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = cpu.mmu.load32(gprs[ARMRegs.SP] + immediate);\n\t\tcpu.mmu.wait32(gprs[ARMRegs.SP] + immediate);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreThumb.prototype.constructLDRB1 = function(rd, rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tvar n = gprs[rn] + immediate;\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = cpu.mmu.loadU8(n);\n\t\tcpu.mmu.wait(n);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreThumb.prototype.constructLDRB2 = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = cpu.mmu.loadU8(gprs[rn] + gprs[rm]);\n\t\tcpu.mmu.wait(gprs[rn] + gprs[rm]);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreThumb.prototype.constructLDRH1 = function(rd, rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tvar n = gprs[rn] + immediate;\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = cpu.mmu.loadU16(n);\n\t\tcpu.mmu.wait(n);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreThumb.prototype.constructLDRH2 = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = cpu.mmu.loadU16(gprs[rn] + gprs[rm]);\n\t\tcpu.mmu.wait(gprs[rn] + gprs[rm]);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreThumb.prototype.constructLDRSB = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = cpu.mmu.load8(gprs[rn] + gprs[rm]);\n\t\tcpu.mmu.wait(gprs[rn] + gprs[rm]);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreThumb.prototype.constructLDRSH = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = cpu.mmu.load16(gprs[rn] + gprs[rm]);\n\t\tcpu.mmu.wait(gprs[rn] + gprs[rm]);\n\t\t++cpu.cycles;\n\t};\n};\n\nARMCoreThumb.prototype.constructLSL1 = function(rd, rm, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tif (immediate == 0) {\n\t\t\tgprs[rd] = gprs[rm];\n\t\t} else {\n\t\t\tcpu.cpsrC = gprs[rm] & (1 << (32 - immediate));\n\t\t\tgprs[rd] = gprs[rm] << immediate;\n\t\t}\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructLSL2 = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar rs = gprs[rm] & 0xFF;\n\t\tif (rs) {\n\t\t\tif (rs < 32) {\n\t\t\t\tcpu.cpsrC = gprs[rd] & (1 << (32 - rs));\n\t\t\t\tgprs[rd] <<= rs;\n\t\t\t} else {\n\t\t\t\tif (rs > 32) {\n\t\t\t\t\tcpu.cpsrC = 0;\n\t\t\t\t} else {\n\t\t\t\t\tcpu.cpsrC = gprs[rd] & 0x00000001;\n\t\t\t\t}\n\t\t\t\tgprs[rd] = 0;\n\t\t\t}\n\t\t}\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructLSR1 = function(rd, rm, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tif (immediate == 0) {\n\t\t\tcpu.cpsrC = gprs[rm] >> 31;\n\t\t\tgprs[rd] = 0;\n\t\t} else {\n\t\t\tcpu.cpsrC = gprs[rm] & (1 << (immediate - 1));\n\t\t\tgprs[rd] = gprs[rm] >>> immediate;\n\t\t}\n\t\tcpu.cpsrN = 0;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n}\n\nARMCoreThumb.prototype.constructLSR2 = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar rs = gprs[rm] & 0xFF;\n\t\tif (rs) {\n\t\t\tif (rs < 32) {\n\t\t\t\tcpu.cpsrC = gprs[rd] & (1 << (rs - 1));\n\t\t\t\tgprs[rd] >>>= rs;\n\t\t\t} else {\n\t\t\t\tif (rs > 32) {\n\t\t\t\t\tcpu.cpsrC = 0;\n\t\t\t\t} else {\n\t\t\t\t\tcpu.cpsrC = gprs[rd] >> 31;\n\t\t\t\t}\n\t\t\t\tgprs[rd] = 0;\n\t\t\t}\n\t\t}\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructMOV1 = function(rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rn] = immediate;\n\t\tcpu.cpsrN = immediate >> 31;\n\t\tcpu.cpsrZ = !(immediate & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructMOV2 = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar d = gprs[rn];\n\t\tcpu.cpsrN = d >> 31;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = 0;\n\t\tcpu.cpsrV = 0;\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreThumb.prototype.constructMOV3 = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = gprs[rm];\n\t};\n};\n\nARMCoreThumb.prototype.constructMUL = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tcpu.mmu.waitMul(gprs[rm]);\n\t\tif ((gprs[rm] & 0xFFFF0000) && (gprs[rd] & 0xFFFF0000)) {\n\t\t\t// Our data type is a double--we'll lose bits if we do it all at once!\n\t\t\tvar hi = ((gprs[rd] & 0xFFFF0000) * gprs[rm]) & 0xFFFFFFFF;\n\t\t\tvar lo = ((gprs[rd] & 0x0000FFFF) * gprs[rm]) & 0xFFFFFFFF;\n\t\t\tgprs[rd] = (hi + lo) & 0xFFFFFFFF;\n\t\t} else {\n\t\t\tgprs[rd] *= gprs[rm];\n\t\t}\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructMVN = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = ~gprs[rm];\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructNEG = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar d = -gprs[rm];\n\t\tcpu.cpsrN = d >> 31;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = 0 >= (d >>> 0);\n\t\tcpu.cpsrV = (gprs[rm] >> 31) && (d >> 31);\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreThumb.prototype.constructORR = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tgprs[rd] = gprs[rd] | gprs[rm];\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructPOP = function(rs, r) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\t++cpu.cycles;\n\t\tvar address = gprs[ARMRegs.SP];\n\t\tvar total = 0;\n\t\tvar m, i;\n\t\tfor (m = 0x01, i = 0; i < 8; m <<= 1, ++i) {\n\t\t\tif (rs & m) {\n\t\t\t\tcpu.mmu.waitSeq32(address);\n\t\t\t\tgprs[i] = cpu.mmu.load32(address);\n\t\t\t\taddress += 4;\n\t\t\t\t++total;\n\t\t\t}\n\t\t}\n\t\tif (r) {\n\t\t\tgprs[ARMRegs.PC] = cpu.mmu.load32(address) & 0xFFFFFFFE;\n\t\t\taddress += 4;\n\t\t\t++total;\n\t\t}\n\t\tcpu.mmu.waitMulti32(address, total);\n\t\tgprs[ARMRegs.SP] = address;\n\t};\n};\n\nARMCoreThumb.prototype.constructPUSH = function(rs, r) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tvar address = gprs[ARMRegs.SP] - 4;\n\t\tvar total = 0;\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tif (r) {\n\t\t\tcpu.mmu.store32(address, gprs[ARMRegs.LR]);\n\t\t\taddress -= 4;\n\t\t\t++total;\n\t\t}\n\t\tvar m, i;\n\t\tfor (m = 0x80, i = 7; m; m >>= 1, --i) {\n\t\t\tif (rs & m) {\n\t\t\t\tcpu.mmu.store32(address, gprs[i]);\n\t\t\t\taddress -= 4;\n\t\t\t\t++total;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tfor (m >>= 1, --i; m; m >>= 1, --i) {\n\t\t\tif (rs & m) {\n\t\t\t\tcpu.mmu.store32(address, gprs[i]);\n\t\t\t\taddress -= 4;\n\t\t\t\t++total;\n\t\t\t}\n\t\t}\n\t\tcpu.mmu.waitMulti32(address, total);\n\t\tgprs[ARMRegs.SP] = address + 4;\n\t};\n};\n\nARMCoreThumb.prototype.constructROR = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar rs = gprs[rm] & 0xFF;\n\t\tif (rs) {\n\t\t\tvar r4 = rs & 0x1F;\n\t\t\tif (r4 > 0) {\n\t\t\t\tcpu.cpsrC = gprs[rd] & (1 << (r4 - 1));\n\t\t\t\tgprs[rd] = (gprs[rd] >>> r4) | (gprs[rd] << (32 - r4));\n\t\t\t} else {\n\t\t\t\tcpu.cpsrC = gprs[rd] >> 31;\n\t\t\t}\n\t\t}\n\t\tcpu.cpsrN = gprs[rd] >> 31;\n\t\tcpu.cpsrZ = !(gprs[rd] & 0xFFFFFFFF);\n\t};\n};\n\nARMCoreThumb.prototype.constructSBC = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar m = (gprs[rm] >>> 0) + (cpu.cpsrC ? 0 : 1);\n\t\tvar d = (gprs[rd] >>> 0) - m;\n\t\tcpu.cpsrN = d >> 31;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = (gprs[rd] >>> 0) >= (d >>> 0);\n\t\tcpu.cpsrV = ((gprs[rd] ^ m) >> 31) && ((gprs[rd] ^ d) >> 31);\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreThumb.prototype.constructSTMIA = function(rn, rs) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.wait(gprs[ARMRegs.PC]);\n\t\tvar address = gprs[rn];\n\t\tvar total = 0;\n\t\tvar m, i;\n\t\tfor (m = 0x01, i = 0; i < 8; m <<= 1, ++i) {\n\t\t\tif (rs & m) {\n\t\t\t\tcpu.mmu.store32(address, gprs[i]);\n\t\t\t\taddress += 4;\n\t\t\t\t++total;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t}\n\t\tfor (m <<= 1, ++i; i < 8; m <<= 1, ++i) {\n\t\t\tif (rs & m) {\n\t\t\t\tcpu.mmu.store32(address, gprs[i]);\n\t\t\t\taddress += 4;\n\t\t\t\t++total;\n\t\t\t}\n\t\t}\n\t\tcpu.mmu.waitMulti32(address, total);\n\t\tgprs[rn] = address;\n\t};\n};\n\nARMCoreThumb.prototype.constructSTR1 = function(rd, rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tvar n = gprs[rn] + immediate;\n\t\tcpu.mmu.store32(n, gprs[rd]);\n\t\tcpu.mmu.wait(gprs[ARMRegs.PC]);\n\t\tcpu.mmu.wait32(n);\n\t};\n};\n\nARMCoreThumb.prototype.constructSTR2 = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.store32(gprs[rn] + gprs[rm], gprs[rd]);\n\t\tcpu.mmu.wait(gprs[ARMRegs.PC]);\n\t\tcpu.mmu.wait32(gprs[rn] + gprs[rm]);\n\t};\n};\n\nARMCoreThumb.prototype.constructSTR3 = function(rd, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.store32(gprs[ARMRegs.SP] + immediate, gprs[rd]);\n\t\tcpu.mmu.wait(gprs[ARMRegs.PC]);\n\t\tcpu.mmu.wait32(gprs[ARMRegs.SP] + immediate);\n\t};\n};\n\nARMCoreThumb.prototype.constructSTRB1 = function(rd, rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tvar n = gprs[rn] + immediate;\n\t\tcpu.mmu.store8(n, gprs[rd]);\n\t\tcpu.mmu.wait(gprs[ARMRegs.PC]);\n\t\tcpu.mmu.wait(n);\n\t};\n};\n\nARMCoreThumb.prototype.constructSTRB2 = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.store8(gprs[rn] + gprs[rm], gprs[rd]);\n\t\tcpu.mmu.wait(gprs[ARMRegs.PC]);\n\t\tcpu.mmu.wait(gprs[rn] + gprs[rm]);\n\t}\n};\n\nARMCoreThumb.prototype.constructSTRH1 = function(rd, rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tvar n = gprs[rn] + immediate;\n\t\tcpu.mmu.store16(n, gprs[rd]);\n\t\tcpu.mmu.wait(gprs[ARMRegs.PC]);\n\t\tcpu.mmu.wait(n);\n\t};\n};\n\nARMCoreThumb.prototype.constructSTRH2 = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.store16(gprs[rn] + gprs[rm], gprs[rd]);\n\t\tcpu.mmu.wait(gprs[ARMRegs.PC]);\n\t\tcpu.mmu.wait(gprs[rn] + gprs[rm]);\n\t}\n};\n\nARMCoreThumb.prototype.constructSUB1 = function(rd, rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar d = gprs[rn] - immediate;\n\t\tcpu.cpsrN = d >> 31;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = (gprs[rn] >>> 0) >= immediate;\n\t\tcpu.cpsrV = (gprs[rn] >> 31) && ((gprs[rn] ^ d) >> 31);\n\t\tgprs[rd] = d;\n\t};\n}\n\nARMCoreThumb.prototype.constructSUB2 = function(rn, immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar d = gprs[rn] - immediate;\n\t\tcpu.cpsrN = d >> 31;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = (gprs[rn] >>> 0) >= immediate;\n\t\tcpu.cpsrV = (gprs[rn] >> 31) && ((gprs[rn] ^ d) >> 31);\n\t\tgprs[rn] = d;\n\t};\n};\n\nARMCoreThumb.prototype.constructSUB3 = function(rd, rn, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar d = gprs[rn] - gprs[rm];\n\t\tcpu.cpsrN = d >> 31;\n\t\tcpu.cpsrZ = !(d & 0xFFFFFFFF);\n\t\tcpu.cpsrC = (gprs[rn] >>> 0) >= (gprs[rm] >>> 0);\n\t\tcpu.cpsrV = (gprs[rn] >> 31) != (gprs[rm] >> 31) &&\n\t\t\t\t\t(gprs[rn] >> 31) != (d >> 31);\n\t\tgprs[rd] = d;\n\t};\n};\n\nARMCoreThumb.prototype.constructSWI = function(immediate) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.irq.swi(immediate);\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t}\n};\n\nARMCoreThumb.prototype.constructTST = function(rd, rm) {\n\tvar cpu : ARMCoreType = this.cpu;\n\tvar gprs = cpu.gprs;\n\treturn function() {\n\t\tcpu.mmu.waitPrefetch(gprs[ARMRegs.PC]);\n\t\tvar aluOut = gprs[rd] & gprs[rm];\n\t\tcpu.cpsrN = aluOut >> 31;\n\t\tcpu.cpsrZ = !(aluOut & 0xFFFFFFFF);\n\t};\n};\n\n///////////////////////////////////////////////////////////////////////////\n\nfunction ARMCore() {\n\tthis.SP = 13;\n\tthis.LR = 14;\n\tthis.PC = 15;\n\n\tthis.MODE_ARM = 0;\n\tthis.MODE_THUMB = 1;\n\n\tthis.MODE_USER = 0x10;\n\tthis.MODE_FIQ = 0x11;\n\tthis.MODE_IRQ = 0x12;\n\tthis.MODE_SUPERVISOR = 0x13;\n\tthis.MODE_ABORT = 0x17;\n\tthis.MODE_UNDEFINED = 0x1B;\n\tthis.MODE_SYSTEM = 0x1F;\n\n\tthis.BANK_NONE = 0\n\tthis.BANK_FIQ = 1;\n\tthis.BANK_IRQ = 2;\n\tthis.BANK_SUPERVISOR = 3;\n\tthis.BANK_ABORT = 4;\n\tthis.BANK_UNDEFINED = 5;\n\n\tthis.WORD_SIZE_ARM = 4;\n\tthis.WORD_SIZE_THUMB = 2;\n\n\tthis.BASE_RESET = 0x00000000;\n\tthis.BASE_UNDEF = 0x00000004;\n\tthis.BASE_SWI = 0x00000008;\n\tthis.BASE_PABT = 0x0000000C;\n\tthis.BASE_DABT = 0x00000010;\n\tthis.BASE_IRQ = 0x00000018;\n\tthis.BASE_FIQ = 0x0000001C;\n\n\tthis.armCompiler = new ARMCoreArm(this);\n\tthis.thumbCompiler = new ARMCoreThumb(this);\n\tthis.generateConds();\n\n\tthis.gprs = new Int32Array(16);\n};\n\nARMCore.prototype.resetCPU = function(startOffset) {\n\tfor (var i = 0; i < ARMRegs.PC; ++i) {\n\t\tthis.gprs[i] = 0;\n\t}\n\tthis.gprs[ARMRegs.PC] = startOffset + ARMConstants.WORD_SIZE_ARM;\n\n\tthis.loadInstruction = this.loadInstructionArm;\n\tthis.execMode = ARMMode.MODE_ARM;\n\tthis.instructionWidth = ARMConstants.WORD_SIZE_ARM;\n\n\tthis.mode = ARMMode.MODE_SYSTEM;\n\n\tthis.cpsrI = false;\n\tthis.cpsrF = false;\n\n\tthis.cpsrV = false;\n\tthis.cpsrC = false;\n\tthis.cpsrZ = false;\n\tthis.cpsrN = false;\n\n\tthis.bankedRegisters = [\n\t\tnew Int32Array(7),\n\t\tnew Int32Array(7),\n\t\tnew Int32Array(2),\n\t\tnew Int32Array(2),\n\t\tnew Int32Array(2),\n\t\tnew Int32Array(2)\n\t];\n\tthis.spsr = 0;\n\tthis.bankedSPSRs = new Int32Array(6);\n\n\tthis.cycles = 0;\n\n\tthis.shifterOperand = 0;\n\tthis.shifterCarryOut = 0;\n\n\tthis.page = null;\n\tthis.pageId = 0;\n\tthis.pageRegion = -1;\n\n\tthis.instruction = null;\n\n\tthis.irq.clear();\n\n\tvar gprs = this.gprs;\n\tvar mmu = this.mmu as ARMMMUInterface;\n\n\tthis.step = function() {\n\t\tvar instruction = this.instruction || (this.instruction = this.loadInstruction(gprs[ARMRegs.PC] - this.instructionWidth));\n\t\tgprs[ARMRegs.PC] += this.instructionWidth;\n\t\tthis.conditionPassed = true;\n\t\tinstruction();\n\n\t\tif (!instruction.writesPC) {\n\t\t\tif (this.instruction != null) { // We might have gotten an interrupt from the instruction\n\t\t\t\tif (instruction.next == null || instruction.next.page.invalid) {\n\t\t\t\t\tinstruction.next = this.loadInstruction(gprs[ARMRegs.PC] - this.instructionWidth);\n\t\t\t\t}\n\t\t\t\tthis.instruction = instruction.next;\n\t\t\t}\n\t\t} else {\n\t\t\tif (this.conditionPassed) {\n\t\t\t\tvar pc = gprs[ARMRegs.PC] &= 0xFFFFFFFE;\n\t\t\t\tif (this.execMode == ARMMode.MODE_ARM) {\n\t\t\t\t\tmmu.wait32(pc);\n\t\t\t\t\tmmu.waitPrefetch32(pc);\n\t\t\t\t} else {\n\t\t\t\t\tmmu.wait(pc);\n\t\t\t\t\tmmu.waitPrefetch(pc);\n\t\t\t\t}\n\t\t\t\tgprs[ARMRegs.PC] += this.instructionWidth;\n\t\t\t\tif (!instruction.fixedJump) {\n\t\t\t\t\tthis.instruction = null;\n\t\t\t\t} else if (this.instruction != null) {\n\t\t\t\t\tif (instruction.next == null || instruction.next.page.invalid) {\n\t\t\t\t\t\tinstruction.next = this.loadInstruction(gprs[ARMRegs.PC] - this.instructionWidth);\n\t\t\t\t\t}\n\t\t\t\t\tthis.instruction = instruction.next;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tthis.instruction = null;\n\t\t\t}\n\t\t}\n\t\tthis.irq.updateTimers();\n\t};\n};\n\nARMCore.prototype.freeze = function() : ARMCoreState {\n\treturn {\n\t\tPC: this.gprs[15] - this.instructionWidth,\n\t\tSP: this.gprs[13],\n\t\t'gprs': [\n\t\t\tthis.gprs[0],\n\t\t\tthis.gprs[1],\n\t\t\tthis.gprs[2],\n\t\t\tthis.gprs[3],\n\t\t\tthis.gprs[4],\n\t\t\tthis.gprs[5],\n\t\t\tthis.gprs[6],\n\t\t\tthis.gprs[7],\n\t\t\tthis.gprs[8],\n\t\t\tthis.gprs[9],\n\t\t\tthis.gprs[10],\n\t\t\tthis.gprs[11],\n\t\t\tthis.gprs[12],\n\t\t\tthis.gprs[13],\n\t\t\tthis.gprs[14],\n\t\t\tthis.gprs[15],\n\t\t],\n\t\t'mode': this.mode,\n\t\t'cpsrI': this.cpsrI,\n\t\t'cpsrF': this.cpsrF,\n\t\t'cpsrV': this.cpsrV,\n\t\t'cpsrC': this.cpsrC,\n\t\t'cpsrZ': this.cpsrZ,\n\t\t'cpsrN': this.cpsrN,\n\t\t'bankedRegisters': [\n\t\t\t[\n\t\t\t\tthis.bankedRegisters[0][0],\n\t\t\t\tthis.bankedRegisters[0][1],\n\t\t\t\tthis.bankedRegisters[0][2],\n\t\t\t\tthis.bankedRegisters[0][3],\n\t\t\t\tthis.bankedRegisters[0][4],\n\t\t\t\tthis.bankedRegisters[0][5],\n\t\t\t\tthis.bankedRegisters[0][6]\n\t\t\t],\n\t\t\t[\n\t\t\t\tthis.bankedRegisters[1][0],\n\t\t\t\tthis.bankedRegisters[1][1],\n\t\t\t\tthis.bankedRegisters[1][2],\n\t\t\t\tthis.bankedRegisters[1][3],\n\t\t\t\tthis.bankedRegisters[1][4],\n\t\t\t\tthis.bankedRegisters[1][5],\n\t\t\t\tthis.bankedRegisters[1][6]\n\t\t\t],\n\t\t\t[\n\t\t\t\tthis.bankedRegisters[2][0],\n\t\t\t\tthis.bankedRegisters[2][1]\n\t\t\t],\n\t\t\t[\n\t\t\t\tthis.bankedRegisters[3][0],\n\t\t\t\tthis.bankedRegisters[3][1]\n\t\t\t],\n\t\t\t[\n\t\t\t\tthis.bankedRegisters[4][0],\n\t\t\t\tthis.bankedRegisters[4][1]\n\t\t\t],\n\t\t\t[\n\t\t\t\tthis.bankedRegisters[5][0],\n\t\t\t\tthis.bankedRegisters[5][1]\n\t\t\t]\n\t\t],\n\t\t'spsr': this.spsr,\n\t\t'bankedSPSRs': [\n\t\t\tthis.bankedSPSRs[0],\n\t\t\tthis.bankedSPSRs[1],\n\t\t\tthis.bankedSPSRs[2],\n\t\t\tthis.bankedSPSRs[3],\n\t\t\tthis.bankedSPSRs[4],\n\t\t\tthis.bankedSPSRs[5]\n\t\t],\n\t\t'cycles': this.cycles,\n\t\t'instructionWidth': this.instructionWidth,\n\t};\n};\n\nARMCore.prototype.defrost = function(frost: ARMCoreState) {\n\tthis.instruction = null;\n\n\tthis.page = null;\n\tthis.pageId = 0;\n\tthis.pageRegion = -1;\n\n\tthis.gprs[0] = frost.gprs[0];\n\tthis.gprs[1] = frost.gprs[1];\n\tthis.gprs[2] = frost.gprs[2];\n\tthis.gprs[3] = frost.gprs[3];\n\tthis.gprs[4] = frost.gprs[4];\n\tthis.gprs[5] = frost.gprs[5];\n\tthis.gprs[6] = frost.gprs[6];\n\tthis.gprs[7] = frost.gprs[7];\n\tthis.gprs[8] = frost.gprs[8];\n\tthis.gprs[9] = frost.gprs[9];\n\tthis.gprs[10] = frost.gprs[10];\n\tthis.gprs[11] = frost.gprs[11];\n\tthis.gprs[12] = frost.gprs[12];\n\tthis.gprs[13] = frost.gprs[13];\n\tthis.gprs[14] = frost.gprs[14];\n\tthis.gprs[15] = frost.gprs[15];\n\n\tthis.mode = frost.mode;\n\tthis.cpsrI = frost.cpsrI;\n\tthis.cpsrF = frost.cpsrF;\n\tthis.cpsrV = frost.cpsrV;\n\tthis.cpsrC = frost.cpsrC;\n\tthis.cpsrZ = frost.cpsrZ;\n\tthis.cpsrN = frost.cpsrN;\n\n\tthis.bankedRegisters[0][0] = frost.bankedRegisters[0][0];\n\tthis.bankedRegisters[0][1] = frost.bankedRegisters[0][1];\n\tthis.bankedRegisters[0][2] = frost.bankedRegisters[0][2];\n\tthis.bankedRegisters[0][3] = frost.bankedRegisters[0][3];\n\tthis.bankedRegisters[0][4] = frost.bankedRegisters[0][4];\n\tthis.bankedRegisters[0][5] = frost.bankedRegisters[0][5];\n\tthis.bankedRegisters[0][6] = frost.bankedRegisters[0][6];\n\n\tthis.bankedRegisters[1][0] = frost.bankedRegisters[1][0];\n\tthis.bankedRegisters[1][1] = frost.bankedRegisters[1][1];\n\tthis.bankedRegisters[1][2] = frost.bankedRegisters[1][2];\n\tthis.bankedRegisters[1][3] = frost.bankedRegisters[1][3];\n\tthis.bankedRegisters[1][4] = frost.bankedRegisters[1][4];\n\tthis.bankedRegisters[1][5] = frost.bankedRegisters[1][5];\n\tthis.bankedRegisters[1][6] = frost.bankedRegisters[1][6];\n\n\tthis.bankedRegisters[2][0] = frost.bankedRegisters[2][0];\n\tthis.bankedRegisters[2][1] = frost.bankedRegisters[2][1];\n\n\tthis.bankedRegisters[3][0] = frost.bankedRegisters[3][0];\n\tthis.bankedRegisters[3][1] = frost.bankedRegisters[3][1];\n\n\tthis.bankedRegisters[4][0] = frost.bankedRegisters[4][0];\n\tthis.bankedRegisters[4][1] = frost.bankedRegisters[4][1];\n\n\tthis.bankedRegisters[5][0] = frost.bankedRegisters[5][0];\n\tthis.bankedRegisters[5][1] = frost.bankedRegisters[5][1];\n\n\tthis.spsr = frost.spsr;\n\tthis.bankedSPSRs[0] = frost.bankedSPSRs[0];\n\tthis.bankedSPSRs[1] = frost.bankedSPSRs[1];\n\tthis.bankedSPSRs[2] = frost.bankedSPSRs[2];\n\tthis.bankedSPSRs[3] = frost.bankedSPSRs[3];\n\tthis.bankedSPSRs[4] = frost.bankedSPSRs[4];\n\tthis.bankedSPSRs[5] = frost.bankedSPSRs[5];\n\n\tthis.cycles = frost.cycles;\n\n\tthis.instructionWidth = frost.instructionWidth;\n\tthis.loadInstruction = frost.instructionWidth == 2 ? this.loadInstructionThumb : this.loadInstructionArm;\n\tthis.execMode = frost.instructionWidth == 2 ? ARMMode.MODE_THUMB : ARMMode.MODE_ARM;\n};\n\nARMCore.prototype.fetchPage = function(address : number) {\n\tvar mmu = this.mmu;\n\tvar region = address >>> mmu.BASE_OFFSET;\n\tvar pageId = mmu.addressToPage(region, address & mmu.OFFSET_MASK);\n\tif (region == this.pageRegion) {\n\t\tif (pageId == this.pageId && !(this.page as ARMMemoryPage).invalid) {\n\t\t\treturn;\n\t\t}\n\t\tthis.pageId = pageId;\n\t} else {\n\t\tthis.pageMask = mmu.memory[region].PAGE_MASK;\n\t\tthis.pageRegion = region;\n\t\tthis.pageId = pageId;\n\t}\n\n\tthis.page = mmu.accessPage(region, pageId);\n};\n\nARMCore.prototype.loadInstructionArm = function(address : number) {\n\tvar next : ARMOperation = null;\n\tthis.fetchPage(address);\n\tvar offset = (address & this.pageMask) >> 2;\n\tnext = (this.page as ARMMemoryPage).arm[offset];\n\tif (next) {\n\t\treturn next;\n\t}\n\tvar instruction = this.mmu.load32(address) >>> 0;\n\tnext = this.compileArm(instruction);\n\tnext.next = null;\n\tnext.page = this.page;\n\tnext.address = address;\n\tnext.opcode = instruction;\n\t(this.page as ARMMemoryPage).arm[offset] = next;\n\treturn next;\n};\n\nARMCore.prototype.loadInstructionThumb = function(address : number) {\n\tvar next : ARMOperation = null;\n\tthis.fetchPage(address);\n\tvar offset = (address & this.pageMask) >> 1;\n\tnext = (this.page as ARMMemoryPage).thumb[offset];\n\tif (next) {\n\t\treturn next;\n\t}\n\tvar instruction = this.mmu.load16(address);\n\tnext = this.compileThumb(instruction);\n\tnext.next = null;\n\tnext.page = this.page;\n\tnext.address = address;\n\tnext.opcode = instruction;\n\t(this.page as ARMMemoryPage).thumb[offset] = next;\n\treturn next;\n};\n\nARMCore.prototype.selectBank = function(mode : ARMMode) {\n\tswitch (mode) {\n\tcase ARMMode.MODE_USER:\n\tcase ARMMode.MODE_SYSTEM:\n\t\t// No banked registers\n\t\treturn ARMConstants.BANK_NONE;\n\tcase ARMMode.MODE_FIQ:\n\t\treturn ARMConstants.BANK_FIQ;\n\tcase ARMMode.MODE_IRQ:\n\t\treturn ARMConstants.BANK_IRQ;\n\tcase ARMMode.MODE_SUPERVISOR:\n\t\treturn ARMConstants.BANK_SUPERVISOR;\n\tcase ARMMode.MODE_ABORT:\n\t\treturn ARMConstants.BANK_ABORT;\n\tcase ARMMode.MODE_UNDEFINED:\n\t\treturn ARMConstants.BANK_UNDEFINED;\n\tdefault:\n\t\tthrow new EmuHalt(\"Invalid user mode \" + mode + \" passed to selectBank\");\n\t}\n};\n\nARMCore.prototype.switchExecMode = function(newMode) {\n\tif (this.execMode != newMode) {\n\t\tthis.execMode = newMode;\n\t\tif (newMode == ARMMode.MODE_ARM) {\n\t\t\tthis.instructionWidth = ARMConstants.WORD_SIZE_ARM;\n\t\t\tthis.loadInstruction = this.loadInstructionArm;\n\t\t} else {\n\t\t\tthis.instructionWidth = ARMConstants.WORD_SIZE_THUMB;\n\t\t\tthis.loadInstruction = this.loadInstructionThumb;\n\t\t}\n\t}\n\t\n};\n\nARMCore.prototype.switchMode = function(newMode) {\n\tif (newMode == this.mode) {\n\t\t// Not switching modes after all\n\t\treturn;\n\t}\n\tif (newMode != ARMMode.MODE_USER || newMode != ARMMode.MODE_SYSTEM) {\n\t\t// Switch banked registers\n\t\tvar newBank = this.selectBank(newMode);\n\t\tvar oldBank = this.selectBank(this.mode);\n\t\tif (newBank != oldBank) {\n\t\t\t// TODO: support FIQ\n\t\t\tif (newMode == ARMMode.MODE_FIQ || this.mode == ARMMode.MODE_FIQ) {\n\t\t\t\tvar oldFiqBank = (oldBank == ARMConstants.BANK_FIQ) ? 1 : 0;\n\t\t\t\tvar newFiqBank = (newBank == ARMConstants.BANK_FIQ) ? 1 : 0;\n\t\t\t\tthis.bankedRegisters[oldFiqBank][2] = this.gprs[8];\n\t\t\t\tthis.bankedRegisters[oldFiqBank][3] = this.gprs[9];\n\t\t\t\tthis.bankedRegisters[oldFiqBank][4] = this.gprs[10];\n\t\t\t\tthis.bankedRegisters[oldFiqBank][5] = this.gprs[11];\n\t\t\t\tthis.bankedRegisters[oldFiqBank][6] = this.gprs[12];\n\t\t\t\tthis.gprs[8] = this.bankedRegisters[newFiqBank][2];\n\t\t\t\tthis.gprs[9] = this.bankedRegisters[newFiqBank][3];\n\t\t\t\tthis.gprs[10] = this.bankedRegisters[newFiqBank][4];\n\t\t\t\tthis.gprs[11] = this.bankedRegisters[newFiqBank][5];\n\t\t\t\tthis.gprs[12] = this.bankedRegisters[newFiqBank][6];\n\t\t\t}\n\t\t\tthis.bankedRegisters[oldBank][0] = this.gprs[ARMRegs.SP];\n\t\t\tthis.bankedRegisters[oldBank][1] = this.gprs[ARMRegs.LR];\n\t\t\tthis.gprs[ARMRegs.SP] = this.bankedRegisters[newBank][0];\n\t\t\tthis.gprs[ARMRegs.LR] = this.bankedRegisters[newBank][1];\n\n\t\t\tthis.bankedSPSRs[oldBank] = this.spsr;\n\t\t\tthis.spsr = this.bankedSPSRs[newBank];\n\t\t}\n\t}\n\tthis.mode = newMode;\n};\n\nARMCore.prototype.packCPSR = function() {\n\treturn this.mode | (this.execMode << 5) | (this.cpsrF << 6) | (this.cpsrI << 7) |\n\t (this.cpsrN << 31) | (this.cpsrZ << 30) | (this.cpsrC << 29) | (this.cpsrV << 28);\n};\n\nARMCore.prototype.unpackCPSR = function(spsr) {\n\tthis.switchMode(spsr & 0x0000001F);\n\tthis.switchExecMode(!!(spsr & 0x00000020));\n\tthis.cpsrF = spsr & 0x00000040;\n\tthis.cpsrI = spsr & 0x00000080;\n\tthis.cpsrN = spsr & 0x80000000;\n\tthis.cpsrZ = spsr & 0x40000000;\n\tthis.cpsrC = spsr & 0x20000000;\n\tthis.cpsrV = spsr & 0x10000000;\n\n\tthis.irq.testIRQ();\n};\n\nARMCore.prototype.hasSPSR = function() {\n\treturn this.mode != ARMMode.MODE_SYSTEM && this.mode != ARMMode.MODE_USER;\n};\n\nARMCore.prototype.raiseIRQ = function() {\n\tif (this.cpsrI) {\n\t\treturn;\n\t}\n\tvar cpsr = this.packCPSR();\n\tvar instructionWidth = this.instructionWidth;\n\tthis.switchMode(ARMMode.MODE_IRQ);\n\tthis.spsr = cpsr;\n\tthis.gprs[ARMRegs.LR] = this.gprs[ARMRegs.PC] - instructionWidth + 4;\n\tthis.gprs[ARMRegs.PC] = this.BASE_IRQ + ARMConstants.WORD_SIZE_ARM;\n\tthis.instruction = null;\n\tthis.switchExecMode(ARMMode.MODE_ARM);\n\tthis.cpsrI = true;\n};\n\nARMCore.prototype.raiseTrap = function() {\n\tvar cpsr = this.packCPSR();\n\tvar instructionWidth = this.instructionWidth;\n\tthis.switchMode(ARMMode.MODE_SUPERVISOR);\n\tthis.spsr = cpsr;\n\tthis.gprs[ARMRegs.LR] = this.gprs[ARMRegs.PC] - instructionWidth;\n\tthis.gprs[ARMRegs.PC] = this.BASE_SWI + ARMConstants.WORD_SIZE_ARM;\n\tthis.instruction = null;\n\tthis.switchExecMode(ARMMode.MODE_ARM);\n\tthis.cpsrI = true;\n};\n\nARMCore.prototype.badOp = function(instruction) {\n\tvar func : AddressFunction = function() {\n\t\tthrow new EmuHalt(\"Illegal instruction: 0x\" + instruction.toString(16));\n\t};\n\tfunc.writesPC = true;\n\tfunc.fixedJump = false;\n\treturn func;\n};\n\nARMCore.prototype.generateConds = function() {\n\tvar cpu = this;\n\tthis.conds = [\n\t\t// EQ\n\t\tfunction() {\n\t\t\treturn cpu.conditionPassed = cpu.cpsrZ;\n\t\t},\n\t\t// NE\n\t\tfunction() {\n\t\t\treturn cpu.conditionPassed = !cpu.cpsrZ;\n\t\t},\n\t\t// CS\n\t\tfunction() {\n\t\t\treturn cpu.conditionPassed = cpu.cpsrC;\n\t\t},\n\t\t// CC\n\t\tfunction() {\n\t\t\treturn cpu.conditionPassed = !cpu.cpsrC;\n\t\t},\n\t\t// MI\n\t\tfunction() {\n\t\t\treturn cpu.conditionPassed = cpu.cpsrN;\n\t\t},\n\t\t// PL\n\t\tfunction() {\n\t\t\treturn cpu.conditionPassed = !cpu.cpsrN;\n\t\t},\n\t\t// VS\n\t\tfunction() {\n\t\t\treturn cpu.conditionPassed = cpu.cpsrV;\n\t\t},\n\t\t// VC\n\t\tfunction() {\n\t\t\treturn cpu.conditionPassed = !cpu.cpsrV;\n\t\t},\n\t\t// HI\n\t\tfunction () {\n\t\t\treturn cpu.conditionPassed = cpu.cpsrC && !cpu.cpsrZ;\n\t\t},\n\t\t// LS\n\t\tfunction () {\n\t\t\treturn cpu.conditionPassed = !cpu.cpsrC || cpu.cpsrZ;\n\t\t},\n\t\t// GE\n\t\tfunction () {\n\t\t\treturn cpu.conditionPassed = !cpu.cpsrN == !cpu.cpsrV;\n\t\t},\n\t\t// LT\n\t\tfunction () {\n\t\t\treturn cpu.conditionPassed = !cpu.cpsrN != !cpu.cpsrV;\n\t\t},\n\t\t// GT\n\t\tfunction () {\n\t\t\treturn cpu.conditionPassed = !cpu.cpsrZ && !cpu.cpsrN == !cpu.cpsrV;\n\t\t},\n\t\t// LE\n\t\tfunction () {\n\t\t\treturn cpu.conditionPassed = cpu.cpsrZ || !cpu.cpsrN != !cpu.cpsrV;\n\t\t},\n\t\t// AL\n\t\tnull,\n\t\tnull\n\t]\n}\n\nARMCore.prototype.barrelShiftImmediate = function(shiftType, immediate, rm) {\n\tvar cpu = this;\n\tvar gprs = this.gprs;\n\tvar shiftOp = this.badOp;\n\tswitch (shiftType) {\n\tcase 0x00000000:\n\t\t// LSL\n\t\tif (immediate) {\n\t\t\tshiftOp = function() {\n\t\t\t\tcpu.shifterOperand = gprs[rm] << immediate;\n\t\t\t\tcpu.shifterCarryOut = gprs[rm] & (1 << (32 - immediate));\n\t\t\t};\n\t\t} else {\n\t\t\t// This boils down to no shift\n\t\t\tshiftOp = function() {\n\t\t\t\tcpu.shifterOperand = gprs[rm];\n\t\t\t\tcpu.shifterCarryOut = cpu.cpsrC;\n\t\t\t};\n\t\t}\n\t\tbreak;\n\tcase 0x00000020:\n\t\t// LSR\n\t\tif (immediate) {\n\t\t\tshiftOp = function() {\n\t\t\t\tcpu.shifterOperand = gprs[rm] >>> immediate;\n\t\t\t\tcpu.shifterCarryOut = gprs[rm] & (1 << (immediate - 1));\n\t\t\t};\n\t\t} else {\n\t\t\tshiftOp = function() {\n\t\t\t\tcpu.shifterOperand = 0;\n\t\t\t\tcpu.shifterCarryOut = gprs[rm] & 0x80000000;\n\t\t\t};\n\t\t}\n\t\tbreak;\n\tcase 0x00000040:\n\t\t// ASR\n\t\tif (immediate) {\n\t\t\tshiftOp = function() {\n\t\t\t\tcpu.shifterOperand = gprs[rm] >> immediate;\n\t\t\t\tcpu.shifterCarryOut = gprs[rm] & (1 << (immediate - 1));\n\t\t\t};\n\t\t} else {\n\t\t\tshiftOp = function() {\n\t\t\t\tcpu.shifterCarryOut = gprs[rm] & 0x80000000;\n\t\t\t\tif (cpu.shifterCarryOut) {\n\t\t\t\t\tcpu.shifterOperand = 0xFFFFFFFF;\n\t\t\t\t} else {\n\t\t\t\t\tcpu.shifterOperand = 0;\n\t\t\t\t}\n\t\t\t};\n\t\t}\n\t\tbreak;\n\tcase 0x00000060:\n\t\t// ROR\n\t\tif (immediate) {\n\t\t\tshiftOp = function() {\n\t\t\t\tcpu.shifterOperand = (gprs[rm] >>> immediate) | (gprs[rm] << (32 - immediate));\n\t\t\t\tcpu.shifterCarryOut = gprs[rm] & (1 << (immediate - 1));\n\t\t\t};\n\t\t} else {\n\t\t\t// RRX\n\t\t\tshiftOp = function() {\n\t\t\t\tcpu.shifterOperand = ((cpu.cpsrC ? 1 : 0) << 31) | (gprs[rm] >>> 1);\n\t\t\t\tcpu.shifterCarryOut = gprs[rm] & 0x00000001;\n\t\t\t};\n\t\t}\n\t\tbreak;\n\t}\n\treturn shiftOp;\n}\n\nARMCore.prototype.compileArm = function(instruction) {\n\tvar op = this.badOp(instruction);\n\tvar i = instruction & 0x0E000000;\n\tvar cpu = this;\n\tvar gprs = this.gprs;\n\n\tvar condOp = this.conds[(instruction & 0xF0000000) >>> 28];\n\tif ((instruction & 0x0FFFFFF0) == 0x012FFF10) {\n\t\t// BX\n\t\tvar rm = instruction & 0xF;\n\t\top = this.armCompiler.constructBX(rm, condOp);\n\t\top.writesPC = true;\n\t\top.fixedJump = false;\n\t} else if (!(instruction & 0x0C000000) && (i == 0x02000000 || (instruction & 0x00000090) != 0x00000090)) {\n\t\tvar opcode = instruction & 0x01E00000;\n\t\tvar s = instruction & 0x00100000;\n\t\tvar shiftsRs = false;\n\t\tif ((opcode & 0x01800000) == 0x01000000 && !s) {\n\t\t\tvar r = instruction & 0x00400000;\n\t\t\tif ((instruction & 0x00B0F000) == 0x0020F000) {\n\t\t\t\t// MSR\n\t\t\t\tvar rm = instruction & 0x0000000F;\n\t\t\t\tvar immediate = instruction & 0x000000FF;\n\t\t\t\tvar rotateImm = (instruction & 0x00000F00) >> 7;\n\t\t\t\timmediate = (immediate >>> rotateImm) | (immediate << (32 - rotateImm));\n\t\t\t\top = this.armCompiler.constructMSR(rm, r, instruction, immediate, condOp);\n\t\t\t\top.writesPC = false;\n\t\t\t} else if ((instruction & 0x00BF0000) == 0x000F0000) {\n\t\t\t\t// MRS\n\t\t\t\tvar rd = (instruction & 0x0000F000) >> 12;\n\t\t\t\top = this.armCompiler.constructMRS(rd, r, condOp);\n\t\t\t\top.writesPC = rd == ARMRegs.PC;\n\t\t\t}\n\t\t} else {\n\t\t\t// Data processing/FSR transfer\n\t\t\tvar rn = (instruction & 0x000F0000) >> 16;\n\t\t\tvar rd = (instruction & 0x0000F000) >> 12;\n\n\t\t\t// Parse shifter operand\n\t\t\tvar shiftType = instruction & 0x00000060;\n\t\t\tvar rm = instruction & 0x0000000F;\n\t\t\tvar shiftOp = function() {\n\t\t\t\tthrow new EmuHalt('BUG: invalid barrel shifter');\n\t\t\t};\n\t\t\tif (instruction & 0x02000000) {\n\t\t\t\tvar immediate = instruction & 0x000000FF;\n\t\t\t\tvar rotate = (instruction & 0x00000F00) >> 7;\n\t\t\t\tif (!rotate) {\n\t\t\t\t\tshiftOp = this.armCompiler.constructAddressingMode1Immediate(immediate);\n\t\t\t\t} else {\n\t\t\t\t\tshiftOp = this.armCompiler.constructAddressingMode1ImmediateRotate(immediate, rotate);\n\t\t\t\t}\n\t\t\t} else if (instruction & 0x00000010) {\n\t\t\t\tvar rs = (instruction & 0x00000F00) >> 8;\n\t\t\t\tshiftsRs = true;\n\t\t\t\tswitch (shiftType) {\n\t\t\t\tcase 0x00000000:\n\t\t\t\t\t// LSL\n\t\t\t\t\tshiftOp = this.armCompiler.constructAddressingMode1LSL(rs, rm);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00000020:\n\t\t\t\t\t// LSR\n\t\t\t\t\tshiftOp = this.armCompiler.constructAddressingMode1LSR(rs, rm);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00000040:\n\t\t\t\t\t// ASR\n\t\t\t\t\tshiftOp = this.armCompiler.constructAddressingMode1ASR(rs, rm);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00000060:\n\t\t\t\t\t// ROR\n\t\t\t\t\tshiftOp = this.armCompiler.constructAddressingMode1ROR(rs, rm);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tvar immediate = (instruction & 0x00000F80) >> 7;\n\t\t\t\tshiftOp = this.barrelShiftImmediate(shiftType, immediate, rm);\n\t\t\t}\n\n\t\t\tswitch (opcode) {\n\t\t\tcase 0x00000000:\n\t\t\t\t// AND\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructANDS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructAND(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x00200000:\n\t\t\t\t// EOR\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructEORS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructEOR(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x00400000:\n\t\t\t\t// SUB\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructSUBS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructSUB(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x00600000:\n\t\t\t\t// RSB\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructRSBS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructRSB(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x00800000:\n\t\t\t\t// ADD\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructADDS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructADD(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x00A00000:\n\t\t\t\t// ADC\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructADCS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructADC(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x00C00000:\n\t\t\t\t// SBC\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructSBCS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructSBC(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x00E00000:\n\t\t\t\t// RSC\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructRSCS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructRSC(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x01000000:\n\t\t\t\t// TST\n\t\t\t\top = this.armCompiler.constructTST(rd, rn, shiftOp, condOp);\n\t\t\t\tbreak;\n\t\t\tcase 0x01200000:\n\t\t\t\t// TEQ\n\t\t\t\top = this.armCompiler.constructTEQ(rd, rn, shiftOp, condOp);\n\t\t\t\tbreak;\n\t\t\tcase 0x01400000:\n\t\t\t\t// CMP\n\t\t\t\top = this.armCompiler.constructCMP(rd, rn, shiftOp, condOp);\n\t\t\t\tbreak;\n\t\t\tcase 0x01600000:\n\t\t\t\t// CMN\n\t\t\t\top = this.armCompiler.constructCMN(rd, rn, shiftOp, condOp);\n\t\t\t\tbreak;\n\t\t\tcase 0x01800000:\n\t\t\t\t// ORR\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructORRS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructORR(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x01A00000:\n\t\t\t\t// MOV\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructMOVS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructMOV(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x01C00000:\n\t\t\t\t// BIC\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructBICS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructBIC(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\tcase 0x01E00000:\n\t\t\t\t// MVN\n\t\t\t\tif (s) {\n\t\t\t\t\top = this.armCompiler.constructMVNS(rd, rn, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructMVN(rd, rn, shiftOp, condOp);\n\t\t\t\t}\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\top.writesPC = rd == ARMRegs.PC;\n\t\t}\n\t} else if ((instruction & 0x0FB00FF0) == 0x01000090) {\n\t\t// Single data swap\n\t\tvar rm = instruction & 0x0000000F;\n\t\tvar rd = (instruction >> 12) & 0x0000000F;\n\t\tvar rn = (instruction >> 16) & 0x0000000F;\n\t\tif (instruction & 0x00400000) {\n\t\t\top = this.armCompiler.constructSWPB(rd, rn, rm, condOp);\n\t\t} else {\n\t\t\top = this.armCompiler.constructSWP(rd, rn, rm, condOp);\n\t\t}\n\t\top.writesPC = rd == ARMRegs.PC;\n\t} else {\n\t\tswitch (i) {\n\t\tcase 0x00000000:\n\t\t\tif ((instruction & 0x010000F0) == 0x00000090) {\n\t\t\t\t// Multiplies\n\t\t\t\tvar rd = (instruction & 0x000F0000) >> 16;\n\t\t\t\tvar rn = (instruction & 0x0000F000) >> 12;\n\t\t\t\tvar rs = (instruction & 0x00000F00) >> 8;\n\t\t\t\tvar rm = instruction & 0x0000000F;\n\t\t\t\tswitch (instruction & 0x00F00000) {\n\t\t\t\tcase 0x00000000:\n\t\t\t\t\t// MUL\n\t\t\t\t\top = this.armCompiler.constructMUL(rd, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00100000:\n\t\t\t\t\t// MULS\n\t\t\t\t\top = this.armCompiler.constructMULS(rd, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00200000:\n\t\t\t\t\t// MLA\n\t\t\t\t\top = this.armCompiler.constructMLA(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak\n\t\t\t\tcase 0x00300000:\n\t\t\t\t\t// MLAS\n\t\t\t\t\top = this.armCompiler.constructMLAS(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00800000:\n\t\t\t\t\t// UMULL\n\t\t\t\t\top = this.armCompiler.constructUMULL(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00900000:\n\t\t\t\t\t// UMULLS\n\t\t\t\t\top = this.armCompiler.constructUMULLS(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00A00000:\n\t\t\t\t\t// UMLAL\n\t\t\t\t\top = this.armCompiler.constructUMLAL(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00B00000:\n\t\t\t\t\t// UMLALS\n\t\t\t\t\top = this.armCompiler.constructUMLALS(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00C00000:\n\t\t\t\t\t// SMULL\n\t\t\t\t\top = this.armCompiler.constructSMULL(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00D00000:\n\t\t\t\t\t// SMULLS\n\t\t\t\t\top = this.armCompiler.constructSMULLS(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00E00000:\n\t\t\t\t\t// SMLAL\n\t\t\t\t\top = this.armCompiler.constructSMLAL(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\tcase 0x00F00000:\n\t\t\t\t\t// SMLALS\n\t\t\t\t\top = this.armCompiler.constructSMLALS(rd, rn, rs, rm, condOp);\n\t\t\t\t\tbreak;\n\t\t\t\t}\n\t\t\t\top.writesPC = rd == ARMRegs.PC;\n\t\t\t} else {\n\t\t\t\t// Halfword and signed byte data transfer\n\t\t\t\tvar load = instruction & 0x00100000;\n\t\t\t\tvar rd = (instruction & 0x0000F000) >> 12;\n\t\t\t\tvar hiOffset = (instruction & 0x00000F00) >> 4;\n\t\t\t\tvar loOffset = rm = instruction & 0x0000000F;\n\t\t\t\tvar h = instruction & 0x00000020;\n\t\t\t\tvar s = instruction & 0x00000040;\n\t\t\t\tvar w = instruction & 0x00200000;\n\t\t\t\tvar i = instruction & 0x00400000;\n\n\t\t\t\tvar address : AddressFunction;\n\t\t\t\tif (i) {\n\t\t\t\t\tvar immediate = loOffset | hiOffset;\n\t\t\t\t\taddress = this.armCompiler.constructAddressingMode23Immediate(instruction, immediate, condOp);\n\t\t\t\t} else {\n\t\t\t\t\taddress = this.armCompiler.constructAddressingMode23Register(instruction, rm, condOp);\n\t\t\t\t}\n\t\t\t\taddress.writesPC = !!w && rn == ARMRegs.PC;\n\n\t\t\t\tif ((instruction & 0x00000090) == 0x00000090) {\n\t\t\t\t\tif (load) {\n\t\t\t\t\t\t// Load [signed] halfword/byte\n\t\t\t\t\t\tif (h) {\n\t\t\t\t\t\t\tif (s) {\n\t\t\t\t\t\t\t\t// LDRSH\n\t\t\t\t\t\t\t\top = this.armCompiler.constructLDRSH(rd, address, condOp);\n\t\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\t\t// LDRH\n\t\t\t\t\t\t\t\top = this.armCompiler.constructLDRH(rd, address, condOp);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t} else {\n\t\t\t\t\t\t\tif (s) {\n\t\t\t\t\t\t\t\t// LDRSB\n\t\t\t\t\t\t\t\top = this.armCompiler.constructLDRSB(rd, address, condOp);\n\t\t\t\t\t\t\t}\n\t\t\t\t\t\t}\n\t\t\t\t\t} else if (!s && h) {\n\t\t\t\t\t\t// STRH\n\t\t\t\t\t\top = this.armCompiler.constructSTRH(rd, address, condOp);\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t\top.writesPC = rd == ARMRegs.PC || address.writesPC;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 0x04000000:\n\t\tcase 0x06000000:\n\t\t\t// LDR/STR\n\t\t\tvar rd = (instruction & 0x0000F000) >> 12;\n\t\t\tvar load = instruction & 0x00100000;\n\t\t\tvar b = instruction & 0x00400000;\n\t\t\tvar i = instruction & 0x02000000;\n\n\t\t\tvar address : AddressFunction = function() {\n\t\t\t\tthrow new EmuHalt(\"Unimplemented memory access: 0x\" + instruction.toString(16));\n\t\t\t};\n\t\t\tif (~instruction & 0x01000000) {\n\t\t\t\t// Clear the W bit if the P bit is clear--we don't support memory translation, so these turn into regular accesses\n\t\t\t\tinstruction &= 0xFFDFFFFF;\n\t\t\t}\n\t\t\tif (i) {\n\t\t\t\t// Register offset\n\t\t\t\tvar rm = instruction & 0x0000000F;\n\t\t\t\tvar shiftType = instruction & 0x00000060;\n\t\t\t\tvar shiftImmediate = (instruction & 0x00000F80) >> 7;\n\t\t\t\t\n\t\t\t\tif (shiftType || shiftImmediate) {\n\t\t\t\t\tshiftOp = this.barrelShiftImmediate(shiftType, shiftImmediate, rm);\n\t\t\t\t\taddress = this.armCompiler.constructAddressingMode2RegisterShifted(instruction, shiftOp, condOp);\n\t\t\t\t} else {\n\t\t\t\t\taddress = this.armCompiler.constructAddressingMode23Register(instruction, rm, condOp);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\t// Immediate\n\t\t\t\tvar offset = instruction & 0x00000FFF;\n\t\t\t\taddress = this.armCompiler.constructAddressingMode23Immediate(instruction, offset, condOp);\n\t\t\t}\n\t\t\tif (load) {\n\t\t\t\tif (b) {\n\t\t\t\t\t// LDRB\n\t\t\t\t\top = this.armCompiler.constructLDRB(rd, address, condOp);\n\t\t\t\t} else {\n\t\t\t\t\t// LDR\n\t\t\t\t\top = this.armCompiler.constructLDR(rd, address, condOp);\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (b) {\n\t\t\t\t\t// STRB\n\t\t\t\t\top = this.armCompiler.constructSTRB(rd, address, condOp);\n\t\t\t\t} else {\n\t\t\t\t\t// STR\n\t\t\t\t\top = this.armCompiler.constructSTR(rd, address, condOp);\n\t\t\t\t}\n\t\t\t}\n\t\t\top.writesPC = load && (rd == ARMRegs.PC || address.writesPC); // SEH\n\t\t\tbreak;\n\t\tcase 0x08000000:\n\t\t\t// Block data transfer\n\t\t\tvar load = instruction & 0x00100000;\n\t\t\tvar w = instruction & 0x00200000;\n\t\t\tvar user = instruction & 0x00400000;\n\t\t\tvar u = instruction & 0x00800000;\n\t\t\tvar p = instruction & 0x01000000;\n\t\t\tvar rs = instruction & 0x0000FFFF;\n\t\t\tvar rn = (instruction & 0x000F0000) >> 16;\n\n\t\t\tvar address : AddressFunction;\n\t\t\tvar immediate = 0;\n\t\t\tvar offset = 0;\n\t\t\tvar overlap = false;\n\t\t\tif (u) {\n\t\t\t\tif (p) {\n\t\t\t\t\timmediate = 4;\n\t\t\t\t}\n\t\t\t\tfor (var m = 0x01, i = 0; i < 16; m <<= 1, ++i) {\n\t\t\t\t\tif (rs & m) {\n\t\t\t\t\t\tif (w && i == rn && !offset) {\n\t\t\t\t\t\t\trs &= ~m;\n\t\t\t\t\t\t\timmediate += 4;\n\t\t\t\t\t\t\toverlap = true;\n\t\t\t\t\t\t}\n\t\t\t\t\t\toffset += 4;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t} else {\n\t\t\t\tif (!p) {\n\t\t\t\t\timmediate = 4;\n\t\t\t\t}\n\t\t\t\tfor (var m = 0x01, i = 0; i < 16; m <<= 1, ++i) {\n\t\t\t\t\tif (rs & m) {\n\t\t\t\t\t\tif (w && i == rn && !offset) {\n\t\t\t\t\t\t\trs &= ~m;\n\t\t\t\t\t\t\timmediate += 4;\n\t\t\t\t\t\t\toverlap = true;\n\t\t\t\t\t\t}\n\t\t\t\t\t\timmediate -= 4;\n\t\t\t\t\t\toffset -= 4;\n\t\t\t\t\t}\n\t\t\t\t}\n\t\t\t}\n\t\t\tif (w) {\n\t\t\t\taddress = this.armCompiler.constructAddressingMode4Writeback(immediate, offset, rn, overlap);\n\t\t\t} else {\n\t\t\t\taddress = this.armCompiler.constructAddressingMode4(immediate, rn);\n\t\t\t}\n\t\t\tif (load) {\n\t\t\t\t// LDM\n\t\t\t\tif (user) {\n\t\t\t\t\top = this.armCompiler.constructLDMS(rs, address, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructLDM(rs, address, condOp);\n\t\t\t\t}\n\t\t\t\top.writesPC = !!(rs & (1 << 15));\n\t\t\t} else {\n\t\t\t\t// STM\n\t\t\t\tif (user) {\n\t\t\t\t\top = this.armCompiler.constructSTMS(rs, address, condOp);\n\t\t\t\t} else {\n\t\t\t\t\top = this.armCompiler.constructSTM(rs, address, condOp);\n\t\t\t\t}\n\t\t\t\top.writesPC = false;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 0x0A000000:\n\t\t\t// Branch\n\t\t\tvar immediate = instruction & 0x00FFFFFF;\n\t\t\tif (immediate & 0x00800000) {\n\t\t\t\timmediate |= 0xFF000000;\n\t\t\t}\n\t\t\timmediate <<= 2;\n\t\t\tvar link = instruction & 0x01000000;\n\t\t\tif (link) {\n\t\t\t\top = this.armCompiler.constructBL(immediate, condOp);\n\t\t\t} else {\n\t\t\t\top = this.armCompiler.constructB(immediate, condOp);\n\t\t\t}\n\t\t\top.writesPC = true;\n\t\t\top.fixedJump = true;\n\t\t\tbreak;\n\t\tcase 0x0C000000:\n\t\t\t// Coprocessor data transfer\n\t\t\tbreak;\n\t\tcase 0x0E000000:\n\t\t\t// Coprocessor data operation/SWI\n\t\t\tif ((instruction & 0x0F000000) == 0x0F000000) {\n\t\t\t\t// SWI\n\t\t\t\tvar immediate = (instruction & 0x00FFFFFF);\n\t\t\t\top = this.armCompiler.constructSWI(immediate, condOp);\n\t\t\t\top.writesPC = false;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tthrow new EmuHalt('Bad opcode: 0x' + instruction.toString(16));\n\t\t}\n\t}\n\n\top.execMode = ARMMode.MODE_ARM;\n\top.fixedJump = op.fixedJump || false;\n\treturn op;\n};\n\nARMCore.prototype.compileThumb = function(instruction) {\n\tvar op = this.badOp(instruction & 0xFFFF);\n\tvar cpu = this;\n\tvar gprs = this.gprs;\n\tif ((instruction & 0xFC00) == 0x4000) {\n\t\t// Data-processing register\n\t\tvar rm = (instruction & 0x0038) >> 3;\n\t\tvar rd = instruction & 0x0007;\n\t\tswitch (instruction & 0x03C0) {\n\t\tcase 0x0000:\n\t\t\t// AND\n\t\t\top = this.thumbCompiler.constructAND(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0040:\n\t\t\t// EOR\n\t\t\top = this.thumbCompiler.constructEOR(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0080:\n\t\t\t// LSL(2)\n\t\t\top = this.thumbCompiler.constructLSL2(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x00C0:\n\t\t\t// LSR(2)\n\t\t\top = this.thumbCompiler.constructLSR2(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0100:\n\t\t\t// ASR(2)\n\t\t\top = this.thumbCompiler.constructASR2(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0140:\n\t\t\t// ADC\n\t\t\top = this.thumbCompiler.constructADC(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0180:\n\t\t\t// SBC\n\t\t\top = this.thumbCompiler.constructSBC(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x01C0:\n\t\t\t// ROR\n\t\t\top = this.thumbCompiler.constructROR(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0200:\n\t\t\t// TST\n\t\t\top = this.thumbCompiler.constructTST(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0240:\n\t\t\t// NEG\n\t\t\top = this.thumbCompiler.constructNEG(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0280:\n\t\t\t// CMP(2)\n\t\t\top = this.thumbCompiler.constructCMP2(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x02C0:\n\t\t\t// CMN\n\t\t\top = this.thumbCompiler.constructCMN(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0300:\n\t\t\t// ORR\n\t\t\top = this.thumbCompiler.constructORR(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0340:\n\t\t\t// MUL\n\t\t\top = this.thumbCompiler.constructMUL(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x0380:\n\t\t\t// BIC\n\t\t\top = this.thumbCompiler.constructBIC(rd, rm);\n\t\t\tbreak;\n\t\tcase 0x03C0:\n\t\t\t// MVN\n\t\t\top = this.thumbCompiler.constructMVN(rd, rm);\n\t\t\tbreak;\n\t\t}\n\t\top.writesPC = false;\n\t} else if ((instruction & 0xFC00) == 0x4400) {\n\t\t// Special data processing / branch/exchange instruction set\n\t\tvar rm = (instruction & 0x0078) >> 3;\n\t\tvar rn = instruction & 0x0007;\n\t\tvar h1 = instruction & 0x0080;\n\t\tvar rd = rn | (h1 >> 4);\n\t\tswitch (instruction & 0x0300) {\n\t\tcase 0x0000:\n\t\t\t// ADD(4)\n\t\t\top = this.thumbCompiler.constructADD4(rd, rm)\n\t\t\top.writesPC = rd == ARMRegs.PC;\n\t\t\tbreak;\n\t\tcase 0x0100:\n\t\t\t// CMP(3)\n\t\t\top = this.thumbCompiler.constructCMP3(rd, rm);\n\t\t\top.writesPC = false;\n\t\t\tbreak;\n\t\tcase 0x0200:\n\t\t\t// MOV(3)\n\t\t\top = this.thumbCompiler.constructMOV3(rd, rm);\n\t\t\top.writesPC = rd == ARMRegs.PC;\n\t\t\tbreak;\n\t\tcase 0x0300:\n\t\t\t// BX\n\t\t\top = this.thumbCompiler.constructBX(rd, rm);\n\t\t\top.writesPC = true;\n\t\t\top.fixedJump = false;\n\t\t\tbreak;\n\t\t}\n\t} else if ((instruction & 0xF800) == 0x1800) {\n\t\t// Add/subtract\n\t\tvar rm = (instruction & 0x01C0) >> 6;\n\t\tvar rn = (instruction & 0x0038) >> 3;\n\t\tvar rd = instruction & 0x0007;\n\t\tswitch (instruction & 0x0600) {\n\t\tcase 0x0000:\n\t\t\t// ADD(3)\n\t\t\top = this.thumbCompiler.constructADD3(rd, rn, rm);\n\t\t\tbreak;\n\t\tcase 0x0200:\n\t\t\t// SUB(3)\n\t\t\top = this.thumbCompiler.constructSUB3(rd, rn, rm);\n\t\t\tbreak;\n\t\tcase 0x0400:\n\t\t\tvar immediate = (instruction & 0x01C0) >> 6;\n\t\t\tif (immediate) {\n\t\t\t\t// ADD(1)\n\t\t\t\top = this.thumbCompiler.constructADD1(rd, rn, immediate);\n\t\t\t} else {\n\t\t\t\t// MOV(2)\n\t\t\t\top = this.thumbCompiler.constructMOV2(rd, rn, rm);\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 0x0600:\n\t\t\t// SUB(1)\n\t\t\tvar immediate = (instruction & 0x01C0) >> 6;\n\t\t\top = this.thumbCompiler.constructSUB1(rd, rn, immediate);\n\t\t\tbreak;\n\t\t}\n\t\top.writesPC = false;\n\t} else if (!(instruction & 0xE000)) {\n\t\t// Shift by immediate\n\t\tvar rd = instruction & 0x0007;\n\t\tvar rm = (instruction & 0x0038) >> 3;\n\t\tvar immediate = (instruction & 0x07C0) >> 6;\n\t\tswitch (instruction & 0x1800) {\n\t\tcase 0x0000:\n\t\t\t// LSL(1)\n\t\t\top = this.thumbCompiler.constructLSL1(rd, rm, immediate);\n\t\t\tbreak;\n\t\tcase 0x0800:\n\t\t\t// LSR(1)\n\t\t\top = this.thumbCompiler.constructLSR1(rd, rm, immediate);\n\t\t\tbreak;\n\t\tcase 0x1000:\n\t\t\t// ASR(1)\n\t\t\top = this.thumbCompiler.constructASR1(rd, rm, immediate);\n\t\t\tbreak;\n\t\tcase 0x1800:\n\t\t\tbreak;\n\t\t}\n\t\top.writesPC = false;\n\t} else if ((instruction & 0xE000) == 0x2000) {\n\t\t// Add/subtract/compare/move immediate\n\t\tvar immediate = instruction & 0x00FF;\n\t\tvar rn = (instruction & 0x0700) >> 8;\n\t\tswitch (instruction & 0x1800) {\n\t\tcase 0x0000:\n\t\t\t// MOV(1)\n\t\t\top = this.thumbCompiler.constructMOV1(rn, immediate);\n\t\t\tbreak;\n\t\tcase 0x0800:\n\t\t\t// CMP(1)\n\t\t\top = this.thumbCompiler.constructCMP1(rn, immediate);\n\t\t\tbreak;\n\t\tcase 0x1000:\n\t\t\t// ADD(2)\n\t\t\top = this.thumbCompiler.constructADD2(rn, immediate);\n\t\t\tbreak;\n\t\tcase 0x1800:\n\t\t\t// SUB(2)\n\t\t\top = this.thumbCompiler.constructSUB2(rn, immediate);\n\t\t\tbreak;\n\t\t}\n\t\top.writesPC = false;\n\t} else if ((instruction & 0xF800) == 0x4800) {\n\t\t// LDR(3)\n\t\tvar rd = (instruction & 0x0700) >> 8;\n\t\tvar immediate = (instruction & 0x00FF) << 2;\n\t\top = this.thumbCompiler.constructLDR3(rd, immediate);\n\t\top.writesPC = false;\n\t} else if ((instruction & 0xF000) == 0x5000) {\n\t\t// Load and store with relative offset\n\t\tvar rd = instruction & 0x0007;\n\t\tvar rn = (instruction & 0x0038) >> 3;\n\t\tvar rm = (instruction & 0x01C0) >> 6;\n\t\tvar opcode = instruction & 0x0E00;\n\t\tswitch (opcode) {\n\t\tcase 0x0000:\n\t\t\t// STR(2)\n\t\t\top = this.thumbCompiler.constructSTR2(rd, rn, rm);\n\t\t\tbreak;\n\t\tcase 0x0200:\n\t\t\t// STRH(2)\n\t\t\top = this.thumbCompiler.constructSTRH2(rd, rn, rm);\n\t\t\tbreak;\n\t\tcase 0x0400:\n\t\t\t// STRB(2)\n\t\t\top = this.thumbCompiler.constructSTRB2(rd, rn, rm);\n\t\t\tbreak;\n\t\tcase 0x0600:\n\t\t\t// LDRSB\n\t\t\top = this.thumbCompiler.constructLDRSB(rd, rn, rm);\n\t\t\tbreak;\n\t\tcase 0x0800:\n\t\t\t// LDR(2)\n\t\t\top = this.thumbCompiler.constructLDR2(rd, rn, rm);\n\t\t\tbreak;\n\t\tcase 0x0A00:\n\t\t\t// LDRH(2)\n\t\t\top = this.thumbCompiler.constructLDRH2(rd, rn, rm);\n\t\t\tbreak;\n\t\tcase 0x0C00:\n\t\t\t// LDRB(2)\n\t\t\top = this.thumbCompiler.constructLDRB2(rd, rn, rm);\n\t\t\tbreak;\n\t\tcase 0x0E00:\n\t\t\t// LDRSH\n\t\t\top = this.thumbCompiler.constructLDRSH(rd, rn, rm);\n\t\t\tbreak;\n\t\t}\n\t\top.writesPC = false;\n\t} else if ((instruction & 0xE000) == 0x6000) {\n\t\t// Load and store with immediate offset\n\t\tvar rd = instruction & 0x0007;\n\t\tvar rn = (instruction & 0x0038) >> 3;\n\t\tvar immediate = (instruction & 0x07C0) >> 4;\n\t\tvar b = instruction & 0x1000;\n\t\tif (b) {\n\t\t\timmediate >>= 2;\n\t\t}\n\t\tvar load = instruction & 0x0800;\n\t\tif (load) {\n\t\t\tif (b) {\n\t\t\t\t// LDRB(1)\n\t\t\t\top = this.thumbCompiler.constructLDRB1(rd, rn, immediate);\n\t\t\t} else {\n\t\t\t\t// LDR(1)\n\t\t\t\top = this.thumbCompiler.constructLDR1(rd, rn, immediate);\n\t\t\t}\n\t\t} else {\n\t\t\tif (b) {\n\t\t\t\t// STRB(1)\n\t\t\t\top = this.thumbCompiler.constructSTRB1(rd, rn, immediate);\n\t\t\t} else {\n\t\t\t\t// STR(1)\n\t\t\t\top = this.thumbCompiler.constructSTR1(rd, rn, immediate);\n\t\t\t}\n\t\t}\n\t\top.writesPC = false;\n\t} else if ((instruction & 0xF600) == 0xB400) {\n\t\t// Push and pop registers\n\t\tvar r = !!(instruction & 0x0100);\n\t\tvar rs = instruction & 0x00FF;\n\t\tif (instruction & 0x0800) {\n\t\t\t// POP\n\t\t\top = this.thumbCompiler.constructPOP(rs, r);\n\t\t\top.writesPC = r;\n\t\t\top.fixedJump = false;\n\t\t} else {\n\t\t\t// PUSH\n\t\t\top = this.thumbCompiler.constructPUSH(rs, r);\n\t\t\top.writesPC = false;\n\t\t}\n\t} else if (instruction & 0x8000) {\n\t\tswitch (instruction & 0x7000) {\n\t\tcase 0x0000:\n\t\t\t// Load and store halfword\n\t\t\tvar rd = instruction & 0x0007;\n\t\t\tvar rn = (instruction & 0x0038) >> 3;\n\t\t\tvar immediate = (instruction & 0x07C0) >> 5;\n\t\t\tif (instruction & 0x0800) {\n\t\t\t\t// LDRH(1)\n\t\t\t\top = this.thumbCompiler.constructLDRH1(rd, rn, immediate);\n\t\t\t} else {\n\t\t\t\t// STRH(1)\n\t\t\t\top = this.thumbCompiler.constructSTRH1(rd, rn, immediate);\n\t\t\t}\n\t\t\top.writesPC = false;\n\t\t\tbreak;\n\t\tcase 0x1000:\n\t\t\t// SP-relative load and store\n\t\t\tvar rd = (instruction & 0x0700) >> 8;\n\t\t\tvar immediate = (instruction & 0x00FF) << 2;\n\t\t\tvar load = instruction & 0x0800;\n\t\t\tif (load) {\n\t\t\t\t// LDR(4)\n\t\t\t\top = this.thumbCompiler.constructLDR4(rd, immediate);\n\t\t\t} else {\n\t\t\t\t// STR(3)\n\t\t\t\top = this.thumbCompiler.constructSTR3(rd, immediate);\n\t\t\t}\n\t\t\top.writesPC = false;\n\t\t\tbreak;\n\t\tcase 0x2000:\n\t\t\t// Load address\n\t\t\tvar rd = (instruction & 0x0700) >> 8;\n\t\t\tvar immediate = (instruction & 0x00FF) << 2;\n\t\t\tif (instruction & 0x0800) {\n\t\t\t\t// ADD(6)\n\t\t\t\top = this.thumbCompiler.constructADD6(rd, immediate);\n\t\t\t} else {\n\t\t\t\t// ADD(5)\n\t\t\t\top = this.thumbCompiler.constructADD5(rd, immediate);\n\t\t\t}\n\t\t\top.writesPC = false;\n\t\t\tbreak;\n\t\tcase 0x3000:\n\t\t\t// Miscellaneous\n\t\t\tif (!(instruction & 0x0F00)) {\n\t\t\t\t// Adjust stack pointer\n\t\t\t\t// ADD(7)/SUB(4)\n\t\t\t\tvar b = instruction & 0x0080;\n\t\t\t\tvar immediate = (instruction & 0x7F) << 2;\n\t\t\t\tif (b) {\n\t\t\t\t\timmediate = -immediate;\n\t\t\t\t}\n\t\t\t\top = this.thumbCompiler.constructADD7(immediate)\n\t\t\t\top.writesPC = false;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 0x4000:\n\t\t\t// Multiple load and store\n\t\t\tvar rn = (instruction & 0x0700) >> 8;\n\t\t\tvar rs = instruction & 0x00FF;\n\t\t\tif (instruction & 0x0800) {\n\t\t\t\t// LDMIA\n\t\t\t\top = this.thumbCompiler.constructLDMIA(rn, rs);\n\t\t\t} else {\n\t\t\t\t// STMIA\n\t\t\t\top = this.thumbCompiler.constructSTMIA(rn, rs);\n\t\t\t}\n\t\t\top.writesPC = false;\n\t\t\tbreak;\n\t\tcase 0x5000:\n\t\t\t// Conditional branch\n\t\t\tvar cond = (instruction & 0x0F00) >> 8;\n\t\t\tvar immediate = (instruction & 0x00FF);\n\t\t\tif (cond == 0xF) {\n\t\t\t\t// SWI\n\t\t\t\top = this.thumbCompiler.constructSWI(immediate);\n\t\t\t\top.writesPC = false;\n\t\t\t} else {\n\t\t\t\t// B(1)\n\t\t\t\tif (instruction & 0x0080) {\n\t\t\t\t\timmediate |= 0xFFFFFF00;\n\t\t\t\t}\n\t\t\t\timmediate <<= 1;\n\t\t\t\tvar condOp = this.conds[cond];\n\t\t\t\top = this.thumbCompiler.constructB1(immediate, condOp);\n\t\t\t\top.writesPC = true;\n\t\t\t\top.fixedJump = true;\n\t\t\t}\n\t\t\tbreak;\n\t\tcase 0x6000:\n\t\tcase 0x7000:\n\t\t\t// BL(X)\n\t\t\tvar immediate = instruction & 0x07FF;\n\t\t\tvar h = instruction & 0x1800;\n\t\t\tswitch (h) {\n\t\t\tcase 0x0000:\n\t\t\t\t// B(2)\n\t\t\t\tif (immediate & 0x0400) {\n\t\t\t\t\timmediate |= 0xFFFFF800;\n\t\t\t\t}\n\t\t\t\timmediate <<= 1;\n\t\t\t\top = this.thumbCompiler.constructB2(immediate);\n\t\t\t\top.writesPC = true;\n\t\t\t\top.fixedJump = true;\n\t\t\t\tbreak;\n\t\t\tcase 0x0800:\n\t\t\t\t// BLX (ARMv5T)\n\t\t\t\t/*op = function() {\n\t\t\t\t\tvar pc = gprs[ARMRegs.PC];\n\t\t\t\t\tgprs[ARMRegs.PC] = (gprs[ARMRegs.LR] + (immediate << 1)) & 0xFFFFFFFC;\n\t\t\t\t\tgprs[ARMRegs.LR] = pc - 1;\n\t\t\t\t\tcpu.switchExecMode(cpu.MODE_ARM);\n\t\t\t\t}*/\n\t\t\t\tbreak;\n\t\t\tcase 0x1000:\n\t\t\t\t// BL(1)\n\t\t\t\tif (immediate & 0x0400) {\n\t\t\t\t\timmediate |= 0xFFFFFC00;\n\t\t\t\t}\n\t\t\t\timmediate <<= 12;\n\t\t\t\top = this.thumbCompiler.constructBL1(immediate);\n\t\t\t\top.writesPC = false;\n\t\t\t\tbreak;\n\t\t\tcase 0x1800:\n\t\t\t\t// BL(2)\n\t\t\t\top = this.thumbCompiler.constructBL2(immediate);\n\t\t\t\top.writesPC = true;\n\t\t\t\top.fixedJump = false;\n\t\t\t\tbreak;\n\t\t\t}\n\t\t\tbreak;\n\t\tdefault:\n\t\t\tthrow new EmuHalt(\"Undefined instruction: 0x\" + instruction.toString(16));\n\t\t}\n\t} else {\n\t\tthrow new EmuHalt('Bad opcode: 0x' + instruction.toString(16));\n\t}\n\n\top.execMode = ARMMode.MODE_THUMB;\n\top.fixedJump = op.fixedJump || false;\n\t//console.log(hex(instruction), op);\n\treturn op;\n};\n\n///////////////////////////////////////////////////////////////////////////\n\nexport class ARM32CPU implements CPU, InstructionBased, ARMMMUInterface, ARMIRQInterface, SavesState<ARMCoreState> {\n\n\tcore : ARMCoreType;\n\tbus : Bus;\n\tmemory : ARMMemoryRegion[];\n\n\tBASE_OFFSET = 24;\n\tOFFSET_MASK = 0x00FFFFFF;\n\n\tconstructor() {\n\t\tthis.core = new ARMCore();\n\t\tthis.core.irq = this;\n\t\tthis.core.mmu = this;\n\t\tthis.resetMemory();\n\t}\n\tresetMemory() {\n\t\tthis.memory = []; // TODO\n\t\tfor (var i=0; i<256; i++) {\n\t\t\t// TODO: constant\n\t\t\tvar bits = 10;\n\t\t\tvar size = 0x80000; \n\t\t\tthis.memory[i] = {\n\t\t\t\tPAGE_MASK: (2 << bits) - 1,\n\t\t\t\tICACHE_PAGE_BITS: bits,\n\t\t\t\ticache: new Array() // size >> (bits + 1))\n\t\t\t }; // TODO?\n\t\t}\n\t}\n\tadvanceInsn() : number {\n\t\tvar n = this.core.cycles;\n\t\tthis.core.step();\n\t\tn -= this.core.cycles;\n\t\treturn n > 0 ? n : 1;\n\t}\n\tgetPC(): number {\n\t\treturn this.core.gprs[15] - this.core.instructionWidth;\n\t}\n\tgetSP(): number {\n\t\treturn this.core.gprs[13];\n\t}\n\tisStable(): boolean {\n\t\treturn true; // TODO?\n\t}\n\tconnectMemoryBus(bus: Bus): void {\n\t\tthis.bus = bus;\n\t}\n\treset(): void {\n\t\tthis.resetMemory();\n\t\tthis.core.resetCPU(0);\n\t}\n\tsaveState() : ARMCoreState {\n\t\treturn this.core.freeze();\n\t}\n\tloadState(state: ARMCoreState): void {\n\t\tthis.core.defrost(state);\n\t}\n\n\tload8(a: number): number {\n\t\treturn (this.bus.read(a) << 24) >> 24;\n\t}\n\tloadU8(a: number): number {\n\t\treturn this.bus.read(a) & 0xff;\n\t}\n\tload16(a: number): number {\n\t\treturn (this.loadU16(a) << 16) >> 16;\n\t}\n\tloadU16(a: number): number {\n\t\treturn this.bus.read(a) | (this.bus.read(a+1) << 8);\n\t}\n\tload32(a: number): number {\n\t\tvar v = this.bus.read(a) | (this.bus.read(a+1) << 8) | (this.bus.read(a+2) << 16) | (this.bus.read(a+3) << 24);\n\t\treturn v;\n\t}\n\t// TODO: memory.invalidatePage(maskedOffset);\n\tstore8(a: number, v: number): void {\n\t\tthis.bus.write(a, v & 0xff);\n\t}\n\tstore16(a: number, v: number): void {\n\t\tthis.bus.write(a, v & 0xff);\n\t\tthis.bus.write(a+1, (v >> 8) & 0xff);\n\t}\n\tstore32(a: number, v: number): void {\n\t\tthis.bus.write(a, v & 0xff);\n\t\tthis.bus.write(a+1, (v >> 8) & 0xff);\n\t\tthis.bus.write(a+2, (v >> 16) & 0xff);\n\t\tthis.bus.write(a+3, (v >> 24) & 0xff);\n\t}\n\t// TODO\n\twait(a: number): void {\n\t\t++this.core.cycles;\n\t}\n\twait32(a: number): void {\n\t\t++this.core.cycles;\n\t}\n\twaitSeq32(a: number): void {\n\t\t++this.core.cycles;\n\t}\n\twaitMul(rs: number): void {\n if (((rs & 0xFFFFFF00) == 0xFFFFFF00) || !(rs & 0xFFFFFF00)) {\n\t\t\tthis.core.cycles += 1;\n\t\t} else if (((rs & 0xFFFF0000) == 0xFFFF0000) || !(rs & 0xFFFF0000)) {\n\t\t\t\tthis.core.cycles += 2;\n\t\t} else if (((rs & 0xFF000000) == 0xFF000000) || !(rs & 0xFF000000)) {\n\t\t\t\tthis.core.cycles += 3;\n\t\t} else {\n\t\t\t\tthis.core.cycles += 4;\n\t\t}\n\t}\n\twaitMulti32(a: number, total: number): void {\n\t\tthis.core.cycles += 2;\n\t}\n\twaitPrefetch(a: number): void {\n\t\t++this.core.cycles;\n\t}\n\twaitPrefetch32(a: number): void {\n\t\t++this.core.cycles;\n\t}\n\taddressToPage(region: number, address: number) : number {\n return address >> this.memory[region].ICACHE_PAGE_BITS;\n\t}\n\taccessPage(region: number, pageId: number): ARMMemoryPage {\n\t\tvar memory = this.memory[region];\n\t\tvar page = memory.icache[pageId];\n\t\tif (!page || page.invalid) {\n\t\t\t\tpage = {\n\t\t\t\t\t\tthumb: new Array(1 << (memory.ICACHE_PAGE_BITS)),\n\t\t\t\t\t\tarm: new Array(1 << memory.ICACHE_PAGE_BITS - 1),\n\t\t\t\t\t\tinvalid: false\n\t\t\t\t}\n\t\t\t\tmemory.icache[pageId] = page;\n\t\t}\n\t\treturn page;\n\t}\n\n\tswi(opcode: number): void {\n\t\tthis.core.raiseTrap();\n\t}\n\tswi32(opcode: number): void {\n this.swi(opcode >> 16);\n\t}\n\tclear() : void {\n\t}\n\tupdateTimers() : void {\n\t}\n\ttestIRQ() : void {\n\t}\n\n\tisThumb() : boolean {\n\t\treturn this.core.instructionWidth == 2;\n\t}\n}\n", "\nimport { ARM32CPU, ARMCoreState } from \"../common/cpu/ARM\";\nimport { BasicScanlineMachine, HasSerialIO, SerialEvent, SerialIOInterface } from \"../common/devices\";\nimport { newAddressDecoder, Keys, makeKeycodeMap, newKeyboardHandler, EmuHalt } from \"../common/emu\";\nimport { Debuggable, EmuState } from \"../common/baseplatform\";\nimport { hex, lpad } from \"../common/util\";\n\nvar GBA_KEYCODE_MAP = makeKeycodeMap([\n [Keys.A, 0, 0x1],\n [Keys.B, 0, 0x2],\n [Keys.GP_A, 0, 0x1],\n [Keys.GP_B, 0, 0x2],\n [Keys.SELECT,0, 0x4],\n [Keys.START ,0, 0x8],\n [Keys.RIGHT, 0, 0x10],\n [Keys.LEFT, 0, 0x20],\n [Keys.UP, 0, 0x40],\n [Keys.DOWN, 0, 0x80],\n]);\n\nconst ROM_START = 0x0;\nconst ROM_SIZE = 0x80000;\nconst RAM_START = 0x2000000;\nconst RAM_SIZE = 0x80000;\nconst IO_START = 0x4000000;\nconst IO_SIZE = 0x100;\nconst MAX_SERIAL_CHARS = 1000000;\n\nconst CPU_FREQ = 4000000; // 4 MHz\n\nexport class ARM32Machine extends BasicScanlineMachine implements Debuggable, HasSerialIO {\n\n cpuFrequency = CPU_FREQ; // MHz\n canvasWidth = 160;\n numTotalScanlines = 256;\n numVisibleScanlines = 128;\n cpuCyclesPerLine = Math.floor(CPU_FREQ / (256*60));\n defaultROMSize = 512*1024;\n sampleRate = 1;\n \n cpu: ARM32CPU = new ARM32CPU();\n ram = new Uint8Array(96*1024);\n ram16 = new Uint16Array(this.ram.buffer);\n pixels32 : Uint32Array;\n pixels8 : Uint8Array;\n vidbase : number = 0;\n brightness : number = 255;\n serial : SerialIOInterface;\n serialOut : SerialEvent[];\n serialIn : SerialEvent[];\n\n constructor() {\n super();\n this.connectCPUMemoryBus(this);\n this.handler = newKeyboardHandler(this.inputs, GBA_KEYCODE_MAP);\n }\n\n connectVideo(pixels:Uint32Array) : void {\n super.connectVideo(pixels);\n this.pixels32 = pixels;\n this.pixels8 = new Uint8Array(pixels.buffer);\n }\n\n connectSerialIO(serial: SerialIOInterface) {\n this.serial = serial;\n }\n\n reset() {\n super.reset();\n this.serialOut = [];\n this.serialIn = [];\n }\n\n // TODO: 32-bit bus?\n\n read = newAddressDecoder([\n [ROM_START, ROM_START+ROM_SIZE-1, ROM_SIZE-1, (a) => {\n return this.rom ? this.rom[a] : 0;\n }],\n [RAM_START, RAM_START+RAM_SIZE-1, RAM_SIZE-1, (a) => {\n return this.ram[a];\n }],\n [IO_START, IO_START+IO_SIZE-1, IO_SIZE-1, (a, v) => {\n return this.readIO(a);\n }],\n [0, (1<<31)-1, 0, (a, v) => {\n throw new EmuHalt(`Address read out of bounds: 0x${hex(a)}`);\n }]\n ]);\n\n write = newAddressDecoder([\n [RAM_START, RAM_START+RAM_SIZE-1, RAM_SIZE-1, (a, v) => {\n this.ram[a] = v;\n }],\n [IO_START, IO_START+IO_SIZE-1, IO_SIZE-1, (a, v) => {\n this.writeIO(a, v);\n }],\n ]);\n\n readIO(a : number) : number {\n switch (a) {\n case 0x0:\n return this.inputs[0];\n case 0x40:\n return (this.serial.byteAvailable() ? 0x80 : 0) | (this.serial.clearToSend() ? 0x40 : 0);\n case 0x44:\n let evin = this.serialIn.shift();\n if (evin != null) {\n this.serialOut.push(evin);\n return evin.value;\n } else\n return 0;\n default:\n return 0;\n }\n }\n\n writeIO(a : number, v : number) : void {\n switch (a) {\n case 0x0:\n //this.brightness = v & 0xff;\n break;\n case 0x48:\n if (this.serialOut.length < MAX_SERIAL_CHARS) {\n this.serialOut.push({op:'write', value:v, nbits:8});\n }\n break;\n }\n }\n\n startScanline() {\n }\n\n drawScanline() {\n }\n \n postFrame() {\n var p32 = this.pixels32;\n var vbase = (this.vidbase >> 1) & 0xfffff;\n var mask = this.brightness << 24;\n for (var i=0; i<p32.length; i++) {\n var col = this.ram16[i + vbase];\n // rrrrrgggggbbbbb0 ->\n // 000rrrrr000ggggg000bbbbb00011111111\n p32[i] = mask | ((col&31)<<3) | (((col>>5)&31)<<11) | (((col>>10)&31)<<19);\n }\n }\n\n getDebugCategories() {\n return ['CPU', 'Stack'];\n }\n\n getDebugInfo?(category: string, state: EmuState) : string {\n switch (category) {\n case 'CPU':\n var s = '';\n var c = state.c as ARMCoreState;\n const EXEC_MODE = {2:'Thumb',4:'ARM'};\n const REGNAMES = {15:'PC',14:'LR',13:'SP',12:'IP',11:'FP',9:'SB'};\n for (var i=0; i<16; i++) {\n s += lpad(REGNAMES[i]||'',3) + lpad('r'+i, 5) + ' ' + hex(c.gprs[i],8) + '\\n';\n }\n s += 'Flags ';\n s += c.cpsrN ? \" N\" : \" -\";\n s += c.cpsrV ? \" V\" : \" -\";\n s += c.cpsrF ? \" F\" : \" -\";\n s += c.cpsrZ ? \" Z\" : \" -\";\n s += c.cpsrC ? \" C\" : \" -\";\n s += c.cpsrI ? \" I\" : \" -\";\n s += '\\n';\n s += 'MODE ' + EXEC_MODE[c.instructionWidth] + ' ' + MODE_NAMES[c.mode] + '\\n';\n s += 'SPSR ' + hex(c.spsr,8) + '\\n';\n s += 'cycl ' + c.cycles + '\\n';\n return s;\n }\n }\n\n saveState() {\n var state = super.saveState() as any;\n state.serial = {\n sin: this.serialIn.slice(0),\n sout : this.serialOut.slice(0)\n }\n return state;\n }\n loadState(state) {\n super.loadState(state);\n this.serialIn = state.serial.sin;\n this.serialOut = state.serial.sout;\n }\n}\n\nconst MODE_NAMES = {\n\t0x10: \"USER\",\n 0x11: \"FIQ\",\n 0x12: \"IRQ\",\n 0x13: \"SUPERVISOR\",\n 0x17: \"ABORT\",\n 0x1b: \"UNDEFINED\",\n 0x1f: \"SYSTEM\",\n};\n", "\nimport { BaseDebugPlatform, CpuState, EmuState, Platform, DisasmLine, Debuggable, Machine, BaseMachinePlatform } from \"../common/baseplatform\";\nimport { AnimationTimer, EmuHalt, padBytes, PLATFORMS, RasterVideo } from \"../common/emu\";\nimport { hex, lpad, loadScript } from \"../common/util\";\nimport { ARM32CPU } from \"../common/cpu/ARM\";\nimport { ARM32Machine } from \"../machine/arm32\";\n\ndeclare var uc, cs : any; // Unicorn module\n\nconst ARM32_PRESETS = [\n { id: 'vidfill.vasm', name: 'Video Memory Fill' },\n];\n\nconst SCREEN_WIDTH = 160;\nconst SCREEN_HEIGHT = 128;\nconst ROM_START_ADDR = 0x0;\nconst HIROM_START_ADDR = 0xff800000;\nconst ROM_SIZE = 512*1024;\nconst RAM_START_ADDR = 0x20000000;\nconst RAM_SIZE = 512*1024;\nconst CLOCKS_PER_FRAME = 10000;\n\ninterface ARM32State extends EmuState {\n r: Uint32Array; // registers\n}\n\nexport abstract class BaseARMMachinePlatform<T extends Machine> extends BaseMachinePlatform<T> {\n\n //getOpcodeMetadata = getOpcodeMetadata_z80;\n getToolForFilename(fn: string) {\n if (fn.endsWith('.vasm')) return \"vasmarm\";\n else if (fn.endsWith('.armips')) return \"armips\";\n else return \"vasmarm\";\n }\n getPresets() { return ARM32_PRESETS; }\n getDefaultExtension() { return \".vasm\"; };\n \n }\n \nclass ARM32Platform extends BaseARMMachinePlatform<ARM32Machine> implements Platform {\n\n capstone_arm : any;\n capstone_thumb : any;\n\n async start() {\n super.start();\n console.log(\"Loading Capstone\");\n await loadScript('./lib/capstone-arm.min.js');\n this.capstone_arm = new cs.Capstone(cs.ARCH_ARM, cs.MODE_ARM);\n this.capstone_thumb = new cs.Capstone(cs.ARCH_ARM, cs.MODE_THUMB);\n }\n\n newMachine() { return new ARM32Machine(); }\n readAddress(a) { return this.machine.read(a); }\n getMemoryMap = function() { return { main:[\n {name:'ROM',start:0x0000000,size:0x80000,type:'rom'},\n {name:'RAM',start:0x2000000,size:0x80000,type:'ram'},\n {name:'I/O',start:0x4000000,size:0x100,type:'io'},\n ] } };\n disassemble(pc:number, read:(addr:number)=>number) : DisasmLine {\n var is_thumb = this.machine.cpu.isThumb();\n var capstone = is_thumb ? this.capstone_thumb : this.capstone_arm;\n var buf = [];\n for (var i=0; i<4; i++) {\n buf[i] = read(pc+i);\n }\n var insns = capstone.disasm(buf, pc, 4);\n var i0 = insns && insns[0];\n if (i0) {\n return {\n nbytes: i0.size,\n line: i0.mnemonic + \" \" + i0.op_str,\n isaddr: i0.address > 0\n };\n } else {\n return {\n nbytes: 4,\n line: \"???\",\n isaddr: false\n };\n }\n }\n}\n\n////\n\nPLATFORMS['arm32'] = ARM32Platform;\n"],
"mappings": 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"names": []
}
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