1
0
mirror of https://github.com/sehugg/8bitworkshop.git synced 2024-09-26 16:56:35 +00:00
8bitworkshop/presets/verilog
2021-06-05 23:32:43 -05:00
..
.gitignore
7segment.v
alu.v verilog: added alu.v 2021-05-07 09:50:04 -05:00
ball_absolute.v
ball_paddle.v
ball_slip_counter.v
binary_counter.v
chardisplay.v
clock_divider.v
copperbars.ice verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice 2020-12-28 10:06:50 -06:00
cpu8.v
cpu16.v
cpu6502.v arm32: platform, vasm and armips, unicorn.js 2021-06-05 23:32:43 -05:00
cpu_platform.v
digits10.v
femto8.cfg
femto8.json
femto16.cfg
femto16.json
font_cp437_8x8.ice verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice 2020-12-28 10:06:50 -06:00
font_cp437_8x8.v
framebuf_vpu.v
framebuffer.v
gates.v make sure all presets start with a blank line, looks nicer (tools/checkpresets.py); updated nes 2018-08-14 00:05:02 -04:00
hvsync_generator.v
icestick.pcf
lfsr.v
life.ice verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice 2020-12-28 10:06:50 -06:00
Makefile dasm: fixed macro line parsing, breakpoints 2021-04-08 10:58:02 -05:00
music.v
ntsc.ice verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice 2020-12-28 10:06:50 -06:00
paddles.v
racing_game_cpu.v verilog: added comments 2020-05-13 12:50:16 -05:00
racing_game.v
ram.v updated presets, changed array syntax, ice40 fpga examples 2018-10-08 20:38:39 -04:00
rototexture.ice verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice 2020-12-28 10:06:50 -06:00
scoreboard.v
sharedbuffer.v
skeleton.silice verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice 2020-12-28 10:06:50 -06:00
skeleton.verilator
sound_generator.v
sprite_bitmap.v
sprite_renderer.v
sprite_rotation.v
sprite_scanline_renderer.v updated presets, changed array syntax, ice40 fpga examples 2018-10-08 20:38:39 -04:00
starfield.v
switches.v verilog/switches: Update Player 2 key documentation 2020-02-29 20:41:41 +13:00
tank.v
test2.asm
test_hvsync.v verilog: added comments 2020-05-13 12:50:16 -05:00
test_pattern.ice verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice 2020-12-28 10:06:50 -06:00
test.asm
tile_renderer.v
tile.tga verilog: 32-bit (FFbbggrr) rgb output, testing w/ Silice 2020-12-28 10:06:50 -06:00